From: Sebastien Bourdeauducq Date: Sat, 14 Sep 2013 18:50:27 +0000 (+0200) Subject: dvisampler: do more deserialization with the ISERDES X-Git-Tag: 24jan2021_ls180~2836 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d421aae1a55fe2ec489a4159e1b9a466bb6fe7f1;p=litex.git dvisampler: do more deserialization with the ISERDES --- diff --git a/milkymist/dvisampler/clocking.py b/milkymist/dvisampler/clocking.py index 9fcad685..bcfca52b 100644 --- a/milkymist/dvisampler/clocking.py +++ b/milkymist/dvisampler/clocking.py @@ -10,7 +10,7 @@ class Clocking(Module, AutoCSR): self.locked = Signal() self.serdesstrobe = Signal() self.clock_domains._cd_pix = ClockDomain() - self.clock_domains._cd_pix5x = ClockDomain() + self.clock_domains._cd_pix2x = ClockDomain() self.clock_domains._cd_pix10x = ClockDomain(reset_less=True) ### @@ -27,7 +27,7 @@ class Clocking(Module, AutoCSR): p_CLKIN_PERIOD=26.7, p_CLKFBOUT_MULT=20, p_CLKOUT0_DIVIDE=2, # pix10x - p_CLKOUT1_DIVIDE=4, # pix5x + p_CLKOUT1_DIVIDE=10, # pix2x p_CLKOUT2_DIVIDE=20, # pix p_COMPENSATION="INTERNAL", @@ -38,20 +38,20 @@ class Clocking(Module, AutoCSR): locked_async = Signal() self.specials += [ - Instance("BUFPLL", p_DIVIDE=2, - i_PLLIN=pll_clk0, i_GCLK=ClockSignal("pix5x"), i_LOCKED=pll_locked, + Instance("BUFPLL", p_DIVIDE=5, + i_PLLIN=pll_clk0, i_GCLK=ClockSignal("pix2x"), i_LOCKED=pll_locked, o_IOCLK=self._cd_pix10x.clk, o_LOCK=locked_async, o_SERDESSTROBE=self.serdesstrobe), - Instance("BUFG", i_I=pll_clk1, o_O=self._cd_pix5x.clk), + Instance("BUFG", i_I=pll_clk1, o_O=self._cd_pix2x.clk), Instance("BUFG", i_I=pll_clk2, o_O=self._cd_pix.clk), MultiReg(locked_async, self.locked, "sys") ] self.comb += self._r_locked.status.eq(self.locked) - # sychronize pix+pix5x reset + # sychronize pix+pix2x reset pix_rst_n = 1 for i in range(2): new_pix_rst_n = Signal() self.specials += Instance("FDCE", i_D=pix_rst_n, i_CE=1, i_C=ClockSignal("pix"), i_CLR=~locked_async, o_Q=new_pix_rst_n) pix_rst_n = new_pix_rst_n - self.comb += self._cd_pix.rst.eq(~pix_rst_n), self._cd_pix5x.rst.eq(~pix_rst_n) + self.comb += self._cd_pix.rst.eq(~pix_rst_n), self._cd_pix2x.rst.eq(~pix_rst_n) diff --git a/milkymist/dvisampler/datacapture.py b/milkymist/dvisampler/datacapture.py index 50a92e44..d7888433 100644 --- a/milkymist/dvisampler/datacapture.py +++ b/milkymist/dvisampler/datacapture.py @@ -34,7 +34,7 @@ class DataCapture(Module, AutoCSR): p_COUNTER_WRAPAROUND="STAY_AT_LIMIT", p_DATA_RATE="SDR", i_IDATAIN=pad_se, o_DATAOUT=pad_delayed_master, - i_CLK=ClockSignal("pix5x"), i_IOCLK0=ClockSignal("pix10x"), + i_CLK=ClockSignal("pix2x"), i_IOCLK0=ClockSignal("pix10x"), i_INC=delay_inc, i_CE=delay_ce, i_CAL=delay_master_cal, i_RST=delay_master_rst, o_BUSY=delay_master_busy, @@ -42,44 +42,44 @@ class DataCapture(Module, AutoCSR): self.specials += Instance("IODELAY2", p_SERDES_MODE="SLAVE", p_DELAY_SRC="IDATAIN", p_IDELAY_TYPE="DIFF_PHASE_DETECTOR", - p_COUNTER_WRAPAROUND="STAY_AT_LIMIT", p_DATA_RATE="SDR", + p_COUNTER_WRAPAROUND="WRAPAROUND", p_DATA_RATE="SDR", i_IDATAIN=pad_se, o_DATAOUT=pad_delayed_slave, - i_CLK=ClockSignal("pix5x"), i_IOCLK0=ClockSignal("pix10x"), + i_CLK=ClockSignal("pix2x"), i_IOCLK0=ClockSignal("pix10x"), i_INC=delay_inc, i_CE=delay_ce, i_CAL=delay_slave_cal, i_RST=delay_slave_rst, o_BUSY=delay_slave_busy, i_T=1) - d0 = Signal() - d1 = Signal() + dsr2 = Signal(5) pd_valid = Signal() pd_incdec = Signal() pd_edge = Signal() pd_cascade = Signal() self.specials += Instance("ISERDES2", p_SERDES_MODE="MASTER", - p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=2, + p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=5, p_INTERFACE_TYPE="RETIMED", i_D=pad_delayed_master, - o_Q4=d0, o_Q3=d1, + o_Q4=dsr2[4], o_Q3=dsr2[3], o_Q2=dsr2[2], o_Q1=dsr2[1], i_BITSLIP=0, i_CE0=1, i_RST=0, - i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix5x"), + i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix2x"), i_IOCE=self.serdesstrobe, o_VALID=pd_valid, o_INCDEC=pd_incdec, i_SHIFTIN=pd_edge, o_SHIFTOUT=pd_cascade) self.specials += Instance("ISERDES2", p_SERDES_MODE="SLAVE", - p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=2, + p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=5, p_INTERFACE_TYPE="RETIMED", i_D=pad_delayed_slave, + o_Q4=dsr2[0], i_BITSLIP=0, i_CE0=1, i_RST=0, - i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix5x"), + i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix2x"), i_IOCE=self.serdesstrobe, i_SHIFTIN=pd_cascade, o_SHIFTOUT=pd_edge) @@ -93,7 +93,7 @@ class DataCapture(Module, AutoCSR): too_late.eq(lateness == (2**ntbits - 1)), too_early.eq(lateness == 0) ] - self.sync.pix5x += [ + self.sync.pix2x += [ If(reset_lateness, lateness.eq(2**(ntbits - 1)) ).Elif(~delay_master_busy & ~delay_slave_busy & ~too_late & ~too_early, @@ -103,9 +103,9 @@ class DataCapture(Module, AutoCSR): ] # Delay control - self.submodules.delay_master_done = PulseSynchronizer("pix5x", "sys") + self.submodules.delay_master_done = PulseSynchronizer("pix2x", "sys") delay_master_pending = Signal() - self.sync.pix5x += [ + self.sync.pix2x += [ self.delay_master_done.i.eq(0), If(~delay_master_pending, If(delay_master_cal | delay_ce, delay_master_pending.eq(1)) @@ -116,9 +116,9 @@ class DataCapture(Module, AutoCSR): ) ) ] - self.submodules.delay_slave_done = PulseSynchronizer("pix5x", "sys") + self.submodules.delay_slave_done = PulseSynchronizer("pix2x", "sys") delay_slave_pending = Signal() - self.sync.pix5x += [ + self.sync.pix2x += [ self.delay_slave_done.i.eq(0), If(~delay_slave_pending, If(delay_slave_cal | delay_ce, delay_slave_pending.eq(1)) @@ -130,12 +130,12 @@ class DataCapture(Module, AutoCSR): ) ] - self.submodules.do_delay_master_cal = PulseSynchronizer("sys", "pix5x") - self.submodules.do_delay_master_rst = PulseSynchronizer("sys", "pix5x") - self.submodules.do_delay_slave_cal = PulseSynchronizer("sys", "pix5x") - self.submodules.do_delay_slave_rst = PulseSynchronizer("sys", "pix5x") - self.submodules.do_delay_inc = PulseSynchronizer("sys", "pix5x") - self.submodules.do_delay_dec = PulseSynchronizer("sys", "pix5x") + self.submodules.do_delay_master_cal = PulseSynchronizer("sys", "pix2x") + self.submodules.do_delay_master_rst = PulseSynchronizer("sys", "pix2x") + self.submodules.do_delay_slave_cal = PulseSynchronizer("sys", "pix2x") + self.submodules.do_delay_slave_rst = PulseSynchronizer("sys", "pix2x") + self.submodules.do_delay_inc = PulseSynchronizer("sys", "pix2x") + self.submodules.do_delay_dec = PulseSynchronizer("sys", "pix2x") self.comb += [ delay_master_cal.eq(self.do_delay_master_cal.o), delay_master_rst.eq(self.do_delay_master_rst.o), @@ -174,13 +174,13 @@ class DataCapture(Module, AutoCSR): # Phase detector control self.specials += MultiReg(Cat(too_late, too_early), self._r_phase.status) - self.submodules.do_reset_lateness = PulseSynchronizer("sys", "pix5x") + self.submodules.do_reset_lateness = PulseSynchronizer("sys", "pix2x") self.comb += [ reset_lateness.eq(self.do_reset_lateness.o), self.do_reset_lateness.i.eq(self._r_phase_reset.re) ] - # 2:10 deserialization + # 5:10 deserialization dsr = Signal(10) - self.sync.pix5x += dsr.eq(Cat(dsr[2:], d1, d0)) + self.sync.pix2x += dsr.eq(Cat(dsr[5:], dsr2)) self.sync.pix += self.d.eq(dsr) diff --git a/top.py b/top.py index ba6ae830..03e0b19a 100644 --- a/top.py +++ b/top.py @@ -163,8 +163,8 @@ class SoC(Module): if platform_name == "mixxeo": self.submodules.leds = gpio.GPIOOut(platform.request("user_led")) self.submodules.fb = framebuffer.MixFramebuffer(platform.request("vga"), lasmim_fb0, lasmim_fb1) - self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 2), lasmim_dvi0) - self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 3), lasmim_dvi1) + self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), lasmim_dvi0) + self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), lasmim_dvi1) if platform_name == "m1": self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2))) self.submodules.leds = gpio.GPIOOut(Cat(*[platform.request("user_led", i) for i in range(2)]))