From: Luke Kenneth Casson Leighton Date: Thu, 21 Mar 2019 13:52:46 +0000 (+0000) Subject: add id_wid/mid to FPAddStage1Data X-Git-Tag: ls180-24jan2020~1584 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d42b1876da5d8ca412fc557ff22d166ca6d59587;p=ieee754fpu.git add id_wid/mid to FPAddStage1Data --- diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index cb4108ba..15745cfa 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -840,12 +840,13 @@ class FPAddStage0(FPState, FPID): class FPAddStage1Data: - def __init__(self, width): + def __init__(self, width, id_wid): self.z = FPNumBase(width, False) self.of = Overflow() + self.mid = Signal(id_wid, reset_less=True) def eq(self, i): - return [self.z.eq(i.z), self.of.eq(i.of)] + return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)] @@ -864,7 +865,7 @@ class FPAddStage1Mod(FPState): return FPAddStage0Data(self.width, self.id_wid) def ospec(self): - return FPAddStage1Data(self.width) + return FPAddStage1Data(self.width, self.id_wid) def setup(self, m, in_tot, in_z): """ links module to inputs and outputs @@ -1013,13 +1014,14 @@ class FPNorm1Data: class FPNorm1ModSingle: - def __init__(self, width): + def __init__(self, width, id_wid): self.width = width + self.id_wid = id_wid self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPAddStage1Data(self.width) + return FPAddStage1Data(self.width, self.id_wid) def ospec(self): return FPNorm1Data(self.width) @@ -1263,7 +1265,7 @@ class FPNormToPack(FPState, FPID): """ # Normalisation (chained to input in_z+in_of) - nmod = FPNorm1ModSingle(self.width) + nmod = FPNorm1ModSingle(self.width, self.id_wid) n_out = nmod.ospec() nmod.setup(m, in_z, in_of, n_out.z) m.d.comb += n_out.roundz.eq(nmod.o.roundz)