From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 1 Feb 2009 08:18:13 +0000 (-0800)
Subject: X86: Fix some incorrect register widths.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d432bd13b2f4796a4a9a97831c521ab66aadc414;p=gem5.git

X86: Fix some incorrect register widths.
---

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index a409d1f0f..d46741f00 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -159,7 +159,7 @@ def operands {{
         'CSAttr':        ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
         'MiscRegDest':   ('ControlReg', 'uqw', 'dest', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209),
         'MiscRegSrc1':   ('ControlReg', 'uqw', 'src1', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210),
-        'TscOp':         ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 211),
-        'M5Reg':         ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None, None), 212),
+        'TscOp':         ('ControlReg', 'uqw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 211),
+        'M5Reg':         ('ControlReg', 'uqw', 'MISCREG_M5_REG', (None, None, None), 212),
         'Mem':           ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
 }};