From: lkcl <lkcl@web>
Date: Thu, 7 Sep 2023 23:36:37 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d438359d5afda91068838a5fe17c1d807c3ac4c5;p=libreriscv.git

---

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index 0a2092673..9e41fbeb3 100644
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -24,7 +24,7 @@ to permit arbitrary access to elements, independently on each
 Vector src or dest register. Up to four separate independent REMAPs may be applied
 to the registers of any instruction.
 
-A normal Vector Add:
+A normal Vector Add (no Element-width Overrides):
 
 ```
    for i in range(VL):