From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 21 Aug 2019 16:44:49 +0000 (+0100)
Subject: rename self._intermediate_output
X-Git-Tag: ls180-24jan2020~434
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d4488e2f12023dc86c0766aba89813a4096864ff;p=ieee754fpu.git

rename self._intermediate_output
---

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index b03284ad..2b4f04da 100644
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -1055,7 +1055,7 @@ class Mul8_16_32_64(Elaboratable):
         self.b = Signal(64)
 
         # intermediates (needed for unit tests)
-        self._intermediate_output = Signal(128)
+        self.intermediate_output = Signal(128)
 
         # output
         self.output = Signal(64)
@@ -1142,28 +1142,28 @@ class Mul8_16_32_64(Elaboratable):
         out_part_pts = add_reduce.o.reg_partition_points
 
         m.submodules.add_reduce = add_reduce
-        m.d.comb += self._intermediate_output.eq(add_reduce.o.output)
+        m.d.comb += self.intermediate_output.eq(add_reduce.o.output)
         # create _output_64
         m.submodules.io64 = io64 = IntermediateOut(64, 128, 1)
-        m.d.comb += io64.intermed.eq(self._intermediate_output)
+        m.d.comb += io64.intermed.eq(self.intermediate_output)
         for i in range(8):
             m.d.comb += io64.part_ops[i].eq(out_part_ops[i])
 
         # create _output_32
         m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
-        m.d.comb += io32.intermed.eq(self._intermediate_output)
+        m.d.comb += io32.intermed.eq(self.intermediate_output)
         for i in range(8):
             m.d.comb += io32.part_ops[i].eq(out_part_ops[i])
 
         # create _output_16
         m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
-        m.d.comb += io16.intermed.eq(self._intermediate_output)
+        m.d.comb += io16.intermed.eq(self.intermediate_output)
         for i in range(8):
             m.d.comb += io16.part_ops[i].eq(out_part_ops[i])
 
         # create _output_8
         m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
-        m.d.comb += io8.intermed.eq(self._intermediate_output)
+        m.d.comb += io8.intermed.eq(self.intermediate_output)
         for i in range(8):
             m.d.comb += io8.part_ops[i].eq(out_part_ops[i])
 
@@ -1198,7 +1198,7 @@ if __name__ == "__main__":
     m = Mul8_16_32_64()
     main(m, ports=[m.a,
                    m.b,
-                   m._intermediate_output,
+                   m.intermediate_output,
                    m.output,
                    *m.part_ops,
                    *m.part_pts.values()])
diff --git a/src/ieee754/part_mul_add/test/test_multiply.py b/src/ieee754/part_mul_add/test/test_multiply.py
index e893ecac..27dfae83 100644
--- a/src/ieee754/part_mul_add/test/test_multiply.py
+++ b/src/ieee754/part_mul_add/test/test_multiply.py
@@ -456,7 +456,7 @@ class TestMul8_16_32_64(unittest.TestCase):
         output2, intermediate_output2 = self.simd_mul(a, b, lanes)
         yield Delay(1e-6)
         if gen_or_check == GenOrCheck.Check:
-            intermediate_output = (yield module._intermediate_output)
+            intermediate_output = (yield module.intermediate_output)
             self.assertEqual(intermediate_output,
                              intermediate_output2,
                              f"0x{intermediate_output:X} "
@@ -522,7 +522,7 @@ class TestMul8_16_32_64(unittest.TestCase):
             file_name += f"-{'_'.join(map(repr, register_levels))}"
         ports = [module.a,
                  module.b,
-                 module._intermediate_output,
+                 module.intermediate_output,
                  module.output]
         ports.extend(module.part_ops)
         ports.extend(module.part_pts.values())