From: lkcl <lkcl@web>
Date: Fri, 7 Jul 2023 05:05:07 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d47122fd0c0864c5d0d30eb26d7b361cb6427849;p=libreriscv.git

---

diff --git a/HDL_workflow/HyperRAM.mdwn b/HDL_workflow/HyperRAM.mdwn
index 9e0670b3d..93b6b1e10 100644
--- a/HDL_workflow/HyperRAM.mdwn
+++ b/HDL_workflow/HyperRAM.mdwn
@@ -9,6 +9,7 @@
   <https://ftp.libre-soc.org/W956x8MBYA_64Mb_HyperBus_pSRAM_TFBGA24_datasheet_A01-005_20211208.pdf>
 * Winbond Verilog Model for W956A8MBY:
   <https://www.winbond.com/resource-files/W956x8MBY_verilog_p.zip>
+* VHDL hyperram <https://github.com/MJoergen/HyperRAM>
 
 ```
 from nmigen.resources.memory import HyperRAMResources