From: R Veera Kumar <vklr@vkten.in>
Date: Mon, 22 Nov 2021 01:52:15 +0000 (+0530)
Subject: Add expected state to case_addme_ca_1 in alu_cases unit test
X-Git-Tag: sv_maxu_works-initial~722
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d47846da1de05f62e52c5bee0382dc2a399e96f8;p=openpower-isa.git

Add expected state to case_addme_ca_1 in alu_cases unit test
---

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index ab622d3d..e9353622 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -123,8 +123,17 @@ class ALUTestCase(TestAccumulatorBase):
                 xer = SelectableInt(0, 64)
                 xer[XER_bits['CA']] = 1 # input carry is 1 (differs from above)
                 initial_sprs[special_sprs['XER']] = xer
+                e = ExpectedState(pc=4)
+                e.intregs[16] = value
+                e.ca = 0x3
+                if value == 0x7ffffffff:
+                    e.intregs[6] = 0x7ffffffff
+                else:
+                    e.intregs[6] = 0xffff80000
+                if '.' in choice:
+                    e.crregs[0] = 0x4
                 self.add_case(Program(lst, bigendian),
-                              initial_regs, initial_sprs)
+                              initial_regs, initial_sprs, expected=e)
 
     def case_addme_ca_so_4(self):
         """test of SO being set