From: whitequark <whitequark@whitequark.org>
Date: Mon, 24 Dec 2018 09:30:47 +0000 (+0000)
Subject: back.rtlil: use one $meminit cell, not one per word.
X-Git-Tag: working~129
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d47c1f8a;p=nmigen.git

back.rtlil: use one $meminit cell, not one per word.

This is *far* more efficient.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 7e3fede..bc98975 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -644,21 +644,23 @@ def convert_fragment(builder, fragment, name, top):
                             memories[memory] = module.memory(width=memory.width, size=memory.depth,
                                                              name=memory.name)
                             addr_bits = bits_for(memory.depth)
+                            data_parts = ["{}'".format(memory.width * memory.depth)]
                             for addr in range(memory.depth):
                                 if addr < len(memory.init):
                                     data = memory.init[addr]
                                 else:
                                     data = 0
-                                module.cell("$meminit", ports={
-                                    "\\ADDR": rhs_compiler(ast.Const(addr, addr_bits)),
-                                    "\\DATA": rhs_compiler(ast.Const(data, memory.width)),
-                                }, params={
-                                    "MEMID": memories[memory],
-                                    "ABITS": addr_bits,
-                                    "WIDTH": memory.width,
-                                    "WORDS": 1,
-                                    "PRIORITY": 0,
-                                })
+                                data_parts.append("{:0{}b}".format(data, memory.width))
+                            module.cell("$meminit", ports={
+                                "\\ADDR": rhs_compiler(ast.Const(0, addr_bits)),
+                                "\\DATA": "".join(data_parts),
+                            }, params={
+                                "MEMID": memories[memory],
+                                "ABITS": addr_bits,
+                                "WIDTH": memory.width,
+                                "WORDS": memory.depth,
+                                "PRIORITY": 0,
+                            })
 
                         param_value = memories[memory]