From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 17:51:11 +0000 (-0700)
Subject: Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
X-Git-Tag: working-ls180~1237^2~114
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d47ff7ba8702f9ec76514cbbec1e447c454f5699;p=yosys.git

Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
---

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 296edace9..1a652eb27 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -30,8 +30,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.box))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.lut))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
deleted file mode 100644
index a4182ed63..000000000
--- a/techlibs/xilinx/abc.box
+++ /dev/null
@@ -1,62 +0,0 @@
-# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
-
-# F7BMUX slower than F7AMUX
-# Inputs: I0 I1 S0
-# Outputs: O
-F7BMUX 1 1 3 1
-217 223 296
-
-# Inputs: I0 I1 S0
-# Outputs: O
-MUXF8 2 1 3 1
-104 94 273
-
-# CARRY4 + CARRY4_[ABCD]X
-# Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
-# Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
-#   (NB: carry chain input/output must be last input/output,
-#        swapped with what normally would have been the last
-#        output, here: CI <-> S, CO <-> O
-CARRY4 3 1 10 8
-223 -   -   -   482 -   -   -   -   222
-400 205 -   -   598 407 -   -   -   334
-523 558 226 -   584 556 537 -   -   239
-582 618 330 227 642 615 596 438 -   313
-340 -   -   -   536 379 -   -   -   271
-433 469 -   -   494 465 445 -   -   157
-512 548 292 -   592 540 520 356 -   228
-508 528 378 380 580 526 507 398 385 114
-
-# SLICEM/A6LUT
-# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
-# Outputs: DPO SPO
-RAM64X1D 4 0 15 2
--   -   -   -   -   -   - 124 124 124 124 124 124 - -
-124 124 124 124 124 124 - -   -   -   -   -   124 - -
-
-# SLICEM/A6LUT + F7[AB]MUX
-# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
-# Outputs: DPO SPO
-RAM128X1D 5 0 17 2
--   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
-347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
-
-# Inputs: C CE D R
-# Outputs: Q
-FDRE 6 0 4 1
-- - - -
-
-# Inputs: C CE D S
-# Outputs: Q
-FDSE 7 0 4 1
-- - - -
-
-# Inputs: C CE CLR D
-# Outputs: Q
-FDCE 8 0 4 1
-- - 404 -
-
-# Inputs: C CE D PRE
-# Outputs: Q
-FDPE 9 0 4 1
-- - - 404
diff --git a/techlibs/xilinx/abc.lut b/techlibs/xilinx/abc.lut
deleted file mode 100644
index 3a7dc268d..000000000
--- a/techlibs/xilinx/abc.lut
+++ /dev/null
@@ -1,14 +0,0 @@
-# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
-
-# K	area	delay
-1 	1	124
-2	2	124 235
-3	3	124 235 399
-4	3	124 235 399 490
-5	3	124 235 399 490 620
-6	5	124 235 399 490 620 632
-                # F7BMUX
-7	10	296 420 531 695 756 916 928
-                # F8MUX
-                    # F8MUX+F7BMUX
-8	20	273 569 693 804 968 1029 1189 1201
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
new file mode 100644
index 000000000..a4182ed63
--- /dev/null
+++ b/techlibs/xilinx/abc_xc7.box
@@ -0,0 +1,62 @@
+# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
+
+# F7BMUX slower than F7AMUX
+# Inputs: I0 I1 S0
+# Outputs: O
+F7BMUX 1 1 3 1
+217 223 296
+
+# Inputs: I0 I1 S0
+# Outputs: O
+MUXF8 2 1 3 1
+104 94 273
+
+# CARRY4 + CARRY4_[ABCD]X
+# Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
+# Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
+#   (NB: carry chain input/output must be last input/output,
+#        swapped with what normally would have been the last
+#        output, here: CI <-> S, CO <-> O
+CARRY4 3 1 10 8
+223 -   -   -   482 -   -   -   -   222
+400 205 -   -   598 407 -   -   -   334
+523 558 226 -   584 556 537 -   -   239
+582 618 330 227 642 615 596 438 -   313
+340 -   -   -   536 379 -   -   -   271
+433 469 -   -   494 465 445 -   -   157
+512 548 292 -   592 540 520 356 -   228
+508 528 378 380 580 526 507 398 385 114
+
+# SLICEM/A6LUT
+# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
+# Outputs: DPO SPO
+RAM64X1D 4 0 15 2
+-   -   -   -   -   -   - 124 124 124 124 124 124 - -
+124 124 124 124 124 124 - -   -   -   -   -   124 - -
+
+# SLICEM/A6LUT + F7[AB]MUX
+# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
+# Outputs: DPO SPO
+RAM128X1D 5 0 17 2
+-   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
+347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
+
+# Inputs: C CE D R
+# Outputs: Q
+FDRE 6 0 4 1
+- - - -
+
+# Inputs: C CE D S
+# Outputs: Q
+FDSE 7 0 4 1
+- - - -
+
+# Inputs: C CE CLR D
+# Outputs: Q
+FDCE 8 0 4 1
+- - 404 -
+
+# Inputs: C CE D PRE
+# Outputs: Q
+FDPE 9 0 4 1
+- - - 404
diff --git a/techlibs/xilinx/abc_xc7.lut b/techlibs/xilinx/abc_xc7.lut
new file mode 100644
index 000000000..3a7dc268d
--- /dev/null
+++ b/techlibs/xilinx/abc_xc7.lut
@@ -0,0 +1,14 @@
+# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
+
+# K	area	delay
+1 	1	124
+2	2	124 235
+3	3	124 235 399
+4	3	124 235 399 490
+5	3	124 235 399 490 620
+6	5	124 235 399 490 620 632
+                # F7BMUX
+7	10	296 420 531 695 756 916 928
+                # F8MUX
+                    # F8MUX+F7BMUX
+8	20	273 569 693 804 968 1029 1189 1201
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 69a3d99c2..2308ddadd 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -279,7 +279,7 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_luts")) {
 			if (abc == "abc9")
-				run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : ""));
+				run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W 160" + string(retime ? " -dff" : ""));
 			else if (help_mode)
 				run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
 			else