From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Sep 2022 11:01:29 +0000 (+0100)
Subject: add dummy fixedsync.mdwn pseudocode for lwarx/stbcx. LR/SC operations
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d488afc85a71824bc346642ba0f206f37529220d;p=openpower-isa.git

add dummy fixedsync.mdwn pseudocode for lwarx/stbcx. LR/SC operations
---

diff --git a/openpower/isa.mdwn b/openpower/isa.mdwn
index 6e304b01..1fbbd632 100644
--- a/openpower/isa.mdwn
+++ b/openpower/isa.mdwn
@@ -17,6 +17,7 @@ the pseudo-code for all opcodes in the POWER v3.0B Public Spec
 * [[isa/fixedshift]]
 * [[isa/fixedstore]]
 * [[isa/fixedtrap]]
+* [[isa/fixedsync]]
 * [[isa/sprset]]
 * [[isa/stringldst]]
 * [[isa/system]]
diff --git a/openpower/isa/fixedsync.mdwn b/openpower/isa/fixedsync.mdwn
new file mode 100644
index 00000000..5667c07f
--- /dev/null
+++ b/openpower/isa/fixedsync.mdwn
@@ -0,0 +1,139 @@
+<!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
+
+<!-- Section 4.6 Fixed-point Synchronisation instructions. Pages 865 - 877 -->
+
+# Instruction Synchronise
+
+XL-Form
+
+* isync
+
+Pseudo-code:
+
+    # TODO
+    undefined(0)
+
+Special Registers Altered:
+
+    None
+
+# Load Byte And Reserve Indexed
+
+X-Form
+
+* lbarx RT,RA,RB,EH
+
+Pseudo-code:
+
+    # TODO
+    undefined(0)
+
+Special Registers Altered:
+
+    None
+
+# Load Halfword And Reserve Indexed
+
+X-Form
+
+* lharx RT,RA,RB,EH
+
+Pseudo-code:
+
+    # TODO
+    undefined(0)
+
+Special Registers Altered:
+
+    None
+
+# Load Word And Reserve Indexed
+
+X-Form
+
+* lwarx RT,RA,RB,EH
+
+Pseudo-code:
+
+    # TODO
+    undefined(0)
+
+Special Registers Altered:
+
+    None
+
+# Load Doubleword And Reserve Indexed
+
+X-Form
+
+* ldarx RT,RA,RB,EH
+
+Pseudo-code:
+
+    # TODO
+    undefined(0)
+
+Special Registers Altered:
+
+    None
+
+# Store Byte Conditional Indexed
+
+X-Form
+
+* stbcx. RS,RA,RB
+
+Pseudo-code:
+
+    # TODO
+    undefined(0)
+
+Special Registers Altered:
+
+    CR0
+
+# Store Halfword Conditional Indexed
+
+X-Form
+
+* sthcx. RS,RA,RB
+
+Pseudo-code:
+
+    # TODO
+    undefined(0)
+
+Special Registers Altered:
+
+    CR0
+
+# Store word Conditional Indexed
+
+X-Form
+
+* stwcx. RS,RA,RB
+
+Pseudo-code:
+
+    # TODO
+    undefined(0)
+
+Special Registers Altered:
+
+    CR0
+
+# Store Doubleword Conditional Indexed
+
+X-Form
+
+* stdcx. RS,RA,RB
+
+Pseudo-code:
+
+    # TODO
+    undefined(0)
+
+Special Registers Altered:
+
+    CR0
+