From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Jun 2020 19:36:07 +0000 (+0100)
Subject: experimenting with setting up and testing memory
X-Git-Tag: div_pipeline~521
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d48d4a67f957bcd10dea05c741b7356bbe8ede4b;p=soc.git

experimenting with setting up and testing memory
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 0be4e3d2..acc203c3 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -37,20 +37,20 @@ class Mem:
         self.word_log2 = math.ceil(math.log2(bytes_per_word))
         if not initial_mem:
             return
-        print ("Mem", initial_mem)
+        print ("Sim-Mem", initial_mem, self.bytes_per_word)
         for addr, (val, width) in initial_mem.items():
             self.st(addr, val, width)
 
     def _get_shifter_mask(self, wid, remainder):
-        #shifter = ((self.bytes_per_word - wid) - remainder) * \
-            #8  # bits per byte
-        shifter = remainder * 8 # bits per byte
+        shifter = ((self.bytes_per_word - wid) - remainder) * \
+            8  # bits per byte
         mask = (1 << (wid * 8)) - 1
         print ("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
         return shifter, mask
 
     # TODO: Implement ld/st of lesser width
     def ld(self, address, width=8):
+        print("ld from addr 0x{:x} width {:d}".format(address, width))
         remainder = address & (self.bytes_per_word - 1)
         address = address >> self.word_log2
         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
@@ -58,9 +58,11 @@ class Mem:
             val = self.mem[address]
         else:
             val = 0
+        print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
 
         if width != self.bytes_per_word:
             shifter, mask = self._get_shifter_mask(width, remainder)
+            print ("masking", hex(val), hex(mask<<shifter), shifter)
             val = val & (mask << shifter)
             val >>= shifter
         print("Read 0x{:x} from addr 0x{:x}".format(val, address))
@@ -69,8 +71,8 @@ class Mem:
     def st(self, addr, v, width=8):
         remainder = addr & (self.bytes_per_word - 1)
         addr = addr >> self.word_log2
-        assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
         print("Writing 0x{:x} to addr 0x{:x}/{:x}".format(v, addr, remainder))
+        assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
         if width != self.bytes_per_word:
             if addr in self.mem:
                 val = self.mem[addr]
diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 5e6fe2e9..67e7025f 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -150,8 +150,10 @@ class TestRunner(FHDLTestCase):
                 if self.funit == Function.LDST:
                     mem = l0.mem.mem
                     memlist = []
-                    for i in range(mem.depth):
-                        yield mem._array[i].eq(sim.mem.ld(i*8, 8))
+                    for i in range(mem.depth//2):
+                        data = sim.mem.ld(i*16, 8)
+                        data1 = sim.mem.ld(i*16+8, 8)
+                        yield mem._array[i].eq(data | (data1<<32))
                     print (mem, mem.depth, mem.width)
                     print ("mem init", list(map(hex,memlist)))
 
diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py
index 8716f4cd..dccdaa8c 100644
--- a/src/soc/fu/ldst/test/test_pipe_caller.py
+++ b/src/soc/fu/ldst/test/test_pipe_caller.py
@@ -63,11 +63,16 @@ class LDSTTestCase(FHDLTestCase):
         self.test_data.append(tc)
 
     def test_1_load(self):
-        lst = ["lwz 3, 0(1)"]
+        lst = ["lhz 3, 0(1)"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x0004
         initial_regs[2] = 0x0008
-        initial_mem = {0x0004: (0x1234, 4)}
+        initial_mem = {0x0000: (0x12345678, 8),
+                       0x0008: (0x54321234, 8),
+                       0x0010: (0x87654321, 8),
+                       0x0018: (0xabcdef01, 8),
+                       0x0040: (0x22324252, 8),
+                       0x0048: (0x18283848, 8)}
         self.run_tst_program(Program(lst), initial_regs,
                              initial_mem=initial_mem)