From: Andrew Waterman <andrew@sifive.com>
Date: Fri, 4 May 2018 19:05:33 +0000 (-0700)
Subject: Revert "C.LWSP and C.LDSP with rd=0 are legal instructions"
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d48f107dba6a96fb827cb47fdf290261feadeb35;p=riscv-isa-sim.git

Revert "C.LWSP and C.LDSP with rd=0 are legal instructions"

See https://github.com/riscv/riscv-isa-manual/commit/01190b6ebeb29cfac6783a3e7ce30cd529bf6c59
---

diff --git a/riscv/insns/c_flwsp.h b/riscv/insns/c_flwsp.h
index d1e14fe..79058c4 100644
--- a/riscv/insns/c_flwsp.h
+++ b/riscv/insns/c_flwsp.h
@@ -4,5 +4,6 @@ if (xlen == 32) {
   require_fp;
   WRITE_FRD(f32(MMU.load_uint32(RVC_SP + insn.rvc_lwsp_imm())));
 } else { // c.ldsp
+  require(insn.rvc_rd() != 0);
   WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm()));
 }
diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h
index ed4dcf3..b3d74db 100644
--- a/riscv/insns/c_lwsp.h
+++ b/riscv/insns/c_lwsp.h
@@ -1,2 +1,3 @@
 require_extension('C');
+require(insn.rvc_rd() != 0);
 WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));