From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 24 Oct 2019 07:14:03 +0000 (+0200)
Subject: Add "verific -L"
X-Git-Tag: working-ls180~977
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d49c6b2cba0256573352ae4dd5669e94ef75b60e;p=yosys.git

Add "verific -L"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 9f9eeb764..c68390418 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1939,12 +1939,18 @@ struct VerificPass : public Pass {
 		log("Load the specified VHDL files into Verific.\n");
 		log("\n");
 		log("\n");
-		log("    verific -work <libname> {-sv|-vhdl|...} <hdl-file>\n");
+		log("    verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>\n");
 		log("\n");
 		log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
 		log("(default library when -work is not present: \"work\")\n");
 		log("\n");
 		log("\n");
+		log("    verific [-L <libname>] {-sv|-vhdl|...} <hdl-file>\n");
+		log("\n");
+		log("Look up external definitions in the specified library.\n");
+		log("(-L may be used more than once)\n");
+		log("\n");
+		log("\n");
 		log("    verific -vlog-incdir <directory>..\n");
 		log("\n");
 		log("Add Verilog include directories.\n");
@@ -2158,12 +2164,17 @@ struct VerificPass : public Pass {
 			goto check_error;
 		}
 
+		veri_file::RemoveAllLOptions();
 		for (; argidx < GetSize(args); argidx++)
 		{
 			if (args[argidx] == "-work" && argidx+1 < GetSize(args)) {
 				work = args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-L" && argidx+1 < GetSize(args)) {
+				veri_file::AddLOption(args[++argidx].c_str());
+				continue;
+			}
 			break;
 		}