From: lkcl <lkcl@web>
Date: Sun, 21 Aug 2022 15:38:50 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~806
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d49dfa5a8ab574635826229c858030b896f499eb;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index afe311f56..fd8327225 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -110,10 +110,10 @@ done via the [[SVSTATE SPR|sv/sprs]].
 
 Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise
 
-    setvli   VL=8   : setvl  r5, r0, VL=8
-    setvli.  VL=8   : setvl. r5, r0, VL=8
-    setmvli  MVL=8  : setvl  r0, r0, MVL=8
-    setmvli. MVL=8  : setvl. r0, r0, MVL=8
+    setvli   VL=8   : setvl  r0, r0, VL=8, vf=0, vs=1, ms=0
+    setvli.  VL=8   : setvl. r0, r0, VL=8, vf=0, vs=1, ms=0
+    setmvli  MVL=8  : setvl  r0, r0, MVL=8, vf=0, vs=0, ms=1
+    setmvli. MVL=8  : setvl. r0, r0, MVL=8, vf=0, vs=0, ms=1
 
 Additional pseudo-op for obtaining VL without modifying it (or any state):