From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 14 Apr 2018 00:00:19 +0000 (+0100)
Subject: add reg table
X-Git-Tag: convert-csv-opcode-to-binary~5682
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d49ee865f13f3bfa559e7a45662bb072d207c983;p=libreriscv.git

add reg table
---

diff --git a/alt_rvp.mdwn b/alt_rvp.mdwn
index 2f4b6063c..c920137c4 100644
--- a/alt_rvp.mdwn
+++ b/alt_rvp.mdwn
@@ -1,5 +1,13 @@
 # Lanes
 
+Register table
+
+| reg num | Lane 0 | Lane 1 | Lane 2 | Lane 3 |
+| ------- | ------ | ------ | ------ | ------ |
+| r0      | (31.0) | (31.0) | (31.0) | (31.0) |
+| r1      | (31.0) | (31.0) | (31.0) | (31.0) |
+| r2      | (31.0) | (31.0) | (31.0) | (31.0) |
+
 Example parallel add:
 
     /* XLEN and N are "baked-in" to the hardware */