From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Jul 2019 06:05:48 +0000 (-0700)
Subject: Add one more comment
X-Git-Tag: working-ls180~1208^2~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d4ab43d9403899dcae74a24e71385fd959de98f8;p=yosys.git

Add one more comment
---

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 7c67c7a79..39427cc90 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -197,6 +197,9 @@ module \$__XILINX_SHIFTX (A, B, Y);
       MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));
     end
     else if (A_WIDTH <= 4) begin
+      // Rather than extend with 1'bx which gets flattened to 1'b0
+      // causing the "don't care" status to get lost, extend with MSB
+      // so that we can recognise again later when mapping MUXF78
       wire [4-1:0] Ax = {{(4-A_WIDTH){A[A_WIDTH-1]}}, A};
       \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[1]), .I2(Ax[2]), .I3(Ax[3]), .S0(B[0]), .S1(B[1]), .O(Y));
     end