From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sat, 17 Nov 2012 18:44:25 +0000 (+0100)
Subject: bus/csr: allow specifying existing interface
X-Git-Tag: 24jan2021_ls180~2099^2~781
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d4baac6c0f8241c6807632d62e9e13709141758c;p=litex.git

bus/csr: allow specifying existing interface
---

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 0bce395d..df254348 100644
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -17,9 +17,9 @@ class Interconnect(SimpleInterconnect):
 	pass
 
 class Initiator(PureSimulable):
-	def __init__(self, generator):
+	def __init__(self, generator, bus=Interface()):
 		self.generator = generator
-		self.bus = Interface()
+		self.bus = bus
 		self.transaction = None
 		self.done = False