From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 25 May 2019 19:55:57 +0000 (-0700)
Subject: Revert enable check
X-Git-Tag: yosys-0.9~109^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d4fb6cac7c4c93f868e294dfc95936516813eeac;p=yosys.git

Revert enable check
---

diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index d10cf508f..2abffa2a9 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -385,9 +385,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 	//                            (ii) reset value is same as constant D
 	//                        and (a) has no initial value
 	//                            (b) initial value same as constant D
-	//                        and (1) has no enable signal
-	//                            (2) enable is always active
-	if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const()) && (!sig_e.size() || (sig_d.is_fully_undef() && !has_init))) {
+	if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) {
 		// Q is permanently D
 		mod->connect(sig_q, sig_d);
 		goto delete_dff;