From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 10 Feb 2020 16:31:01 +0000 (-0800)
Subject: Merge pull request #1670 from rodrigomelo9/master
X-Git-Tag: working-ls180~803
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d4ff5b2d007c73cd95fa61bafdb65a47796014d9;p=yosys.git

Merge pull request #1670 from rodrigomelo9/master

$readmem[hb] file inclusion is now relative to the Verilog file
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d4ff5b2d007c73cd95fa61bafdb65a47796014d9