From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 May 2023 18:53:45 +0000 (+0100)
Subject: add links between decode and issue
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d5049cda8780f0d7124f7c426ba935744b7e426c;p=openpower-isa.git

add links between decode and issue
---

diff --git a/src/openpower/cyclemodel/inorder.py b/src/openpower/cyclemodel/inorder.py
index c1f8c057..8d8f5530 100644
--- a/src/openpower/cyclemodel/inorder.py
+++ b/src/openpower/cyclemodel/inorder.py
@@ -15,6 +15,7 @@
 
 """
 
+
 class RegisterWrite(set):
     """RegisterWrite: contains the set of Read-after-Write Hazards.
     Anything in this set must be a STALL at Decode phase because the
@@ -24,6 +25,7 @@ class RegisterWrite(set):
     def write_expected(self, regs): len(self.intersection(regs)) != 0
     def retire_write(self, regs): self.difference_update(regs)
 
+
 class Execute:
     """Execute Pipeline: keeps a countdown-sorted list of instructions
     to expect at a future cycle (tick).  Anything at zero is processed
@@ -85,6 +87,10 @@ class Fetch:
 
 
 class Decode:
+    """Decode: performs a "decode" of the instruction. identifies and records
+    read/write regs. the reads/writes possible should likely not all be here,
+    perhaps split across "Issue"?
+    """
     def __init__(self, cpu):
         self.stages = [None] # only ever going to be 1 long but hey
         self.cpu = cpu
@@ -110,22 +116,31 @@ class Decode:
         readregs.difference_update(reads_possible)
         # and "Reserves" the writes
         self.cpu.expect_write(writeregs)
+        # now pass the instruction on to Issue
+        self.cpu.issue.add_instruction(insn, writeregs)
         return stall
 
 
 class Issue:
-    """Issue phase: if not stalled will place the instruction into execute
+    """Issue phase: if not stalled will place the instruction into execute.
+    TODO: move the reading and writing of regs here.
     """
     def __init__(self, cpu):
         self.stages = [None] # only ever going to be 1 long but hey
         self.cpu = cpu
 
+    def add_instruction(self, insn, writeregs):
+        # get the read and write regs
+        assert self.stages[0] is None # must be empty (tick or stall)
+        self.stages[0] = (insn, writeregs)
+
     def tick(self):
         self.stages[0] = None
 
     def process_instructions(self, stall):
-        if stall: return
+        if stall: return stall
         self.cpu.execute.add_instructions(self.stages[0])
+        return stall
 
 
 class CPU: