From: lkcl <lkcl@web>
Date: Tue, 29 Mar 2022 13:53:23 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2952
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d50eac81b3d8eac04ade01e95f29b1af9b7a7a90;p=libreriscv.git

---

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 14ce3e208..1ee91bdf1 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -2,6 +2,8 @@
 
 # New instructions for CR/INT predication
 
+**DRAFT STATUS**
+
 See:
 
 * main bugreport for crweirds
@@ -64,7 +66,7 @@ the CR Register, not to individual bits within the CR register.
 
 # Instruction form and pseudocode
 
-Instruction format:
+**DRAFT** Instruction format (use of MAJOR 19 not approved):
 
 |0-5|6-10 |11|12-15|16-18|19-20|21-25  |26-30  |31|name      |
 |---|---- |--|-----|-----|-----|-----  |-----  |--|----      |