From: Neel <neelgala@gmail.com>
Date: Wed, 25 Jul 2018 09:34:30 +0000 (+0530)
Subject: adding master and slave interface to rgbtll
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d51d1c5274e7883b2f5bca6b57a095cc1bfbcc69;p=shakti-peripherals.git

adding master and slave interface to rgbtll
---

diff --git a/src/peripherals/rgbttl/Makefile b/src/peripherals/rgbttl/Makefile
new file mode 100644
index 0000000..d112269
--- /dev/null
+++ b/src/peripherals/rgbttl/Makefile
@@ -0,0 +1,53 @@
+### Makefile for the cclass project
+
+TOP_MODULE:=mkrgbttl_dummy
+TOP_FILE:=rgbttl_dummy.bsv
+TOP_DIR:=./
+WORKING_DIR := $(shell pwd)
+
+BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./bsv_lib/
+BSVINCDIR:= $(BSVINCDIR):../../../src/uncore/axi4
+BSVINCDIR:= $(BSVINCDIR):../../../src/uncore/axi4lite
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/gpio
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/rgbttl
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/i2c
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/mux
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/plic
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/pwm
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/qspi
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/spi
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/sdmmc
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/uart
+
+default: gen_verilog
+
+check-blue:
+	@if test -z "$$BLUESPECDIR"; then echo "BLUESPECDIR variable not set"; exit 1; fi; 
+
+###### Setting the variables for bluespec compile #$############################
+BSVCOMPILEOPTS:= -check-assert -suppress-warnings G0020 -keep-fires -opt-undetermined-vals -remove-false-rules -remove-empty-rules -remove-starved-rules 
+BSVLINKOPTS:=-parallel-sim-link 8 -keep-fires
+VERILOGDIR:=./verilog/
+BSVBUILDDIR:=./bsv_build/
+BSVOUTDIR:=./bin
+################################################################################
+
+########## BSIM COMPILE, LINK AND SIMULATE TARGETS ##########################
+.PHONY: check-restore
+check-restore:
+	@if [ "$(define_macros)" != "$(old_define_macros)" ];	then	make clean ;	fi;
+
+.PHONY: gen_verilog 
+gen_verilog: check-restore check-blue 
+	@echo Compiling mkTbSoc in Verilog for simulations ...
+	@mkdir -p $(BSVBUILDDIR); 
+	@mkdir -p $(VERILOGDIR); 
+	bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log
+	@echo Compilation finished
+
+#############################################################################
+
+.PHONY: clean
+clean:
+	rm -rf $(BSVBUILDDIR) *.log $(BSVOUTDIR) ./bbl*
+	rm -rf verilog obj_dir bsv_src
diff --git a/src/peripherals/rgbttl/instance_defines.bsv b/src/peripherals/rgbttl/instance_defines.bsv
new file mode 100644
index 0000000..38780f5
--- /dev/null
+++ b/src/peripherals/rgbttl/instance_defines.bsv
@@ -0,0 +1,24 @@
+`define ADDR 32
+`define PADDR 32
+`define DATA 64
+`define Reg_width 64
+`define USERSPACE 0
+
+// TODO: work out if these are needed
+`define PWM_AXI4Lite
+`define PRFDEPTH 6
+`define VADDR 39
+`define DCACHE_BLOCK_SIZE 4
+`define DCACHE_WORD_SIZE 8
+`define PERFMONITORS                            64
+`define DCACHE_WAYS 4
+`define DCACHE_TAG_BITS 20      // tag_bits = 52
+`define PLIC
+	`define PLICBase		'h0c000000
+	`define PLICEnd		'h10000000
+`define INTERRUPT_PINS 64
+
+`define BAUD_RATE 130
+`ifdef simulate
+  `define BAUD_RATE 5 //130 //
+`endif