From: lkcl Date: Mon, 18 Jan 2021 13:52:26 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~419 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d522fe5188b493bbaf1c08a8ab60e0475ea85b44;p=libreriscv.git --- diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index 96b9dcfd4..83b7d453c 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -172,7 +172,7 @@ Pseudo-op: The name "weird" refers to a minor violation of SV rules when it comes to deriving the Vectorised versions of these instructions. Normally the progression of the SV for-loop would move on to the next register. -Instead however these instructions **remain in the same register** and insert or transfer between **bits** of the scalar integer source or destination. +Instead however in the scalar case these instructions **remain in the same register** and insert or transfer between **bits** of the scalar integer source or destination. crrweird: RT, BB, mask.mode