From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Oct 2020 17:09:48 +0000 (+0100)
Subject: add ports function to DummyPLL
X-Git-Tag: 24jan2021_ls180~204
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d52cd81f6f749574831c6be217ebec5a92f729da;p=soc.git

add ports function to DummyPLL
---

diff --git a/src/soc/clock/select.py b/src/soc/clock/select.py
index 463852cf..23286b7a 100644
--- a/src/soc/clock/select.py
+++ b/src/soc/clock/select.py
@@ -88,6 +88,9 @@ class DummyPLL(Elaboratable):
 
         return m
 
+    def ports(self):
+        return [self.clk_24_i, self.clk_pll_o]
+
 
 if __name__ == '__main__':
     dut = ClockSelect()