From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Tue, 19 Sep 2023 15:44:56 +0000 (+0100)
Subject: Added english description for lhzu instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d53119b479df653818fa84abffec116a1ac4fcb5;p=openpower-isa.git

Added english description for lhzu instruction
---

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 0e2b6536..93297dcc 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -152,9 +152,11 @@ Pseudo-code:
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- EA
 
-Description:Let the effective address (EA) be the sum
-(RA|0)+ (RB). The halfword in storage addressed by
-EA is loaded into RT 48:63. RT 0:47 are set to 0.
+Description:Let the effective address (EA) be the sum (RA)+ D. The
+halfword in storage addressed by EA is loaded into
+RT48:63. RT 0:47 are set to 0.
+EA is placed into register RA.
+If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered: