From: Vincentius Robby <acolyte@umich.edu>
Date: Wed, 20 Jun 2007 18:54:17 +0000 (-0400)
Subject: Removed "adding instead of dividing" trick.
X-Git-Tag: m5_2.0_beta4~326^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d540dde5b4ed38c5aec846282082dd04fce24b78;p=gem5.git

Removed "adding instead of dividing" trick.
Caused slowdown in performance instead of speeding up.

src/cpu/base.cc:
    Removed "adding instead of dividing" trick.
src/mem/bus.cc:
    Fixed spelling in comments.
    Removed "adding instead of dividing" trick.

--HG--
extra : convert_revision : 65a736f4f09a64e737dc7aeee53b117976330488
---

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 078ae1283..f86313da0 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -269,12 +269,10 @@ Tick
 BaseCPU::nextCycle(Tick begin_tick)
 {
     Tick next_tick = begin_tick;
-    next_tick -= (next_tick % clock);
+    if (next_tick % clock != 0)
+        next_tick = next_tick - (next_tick % clock) + clock;
     next_tick += phase;
 
-    while (next_tick < curTick)
-        next_tick += clock;
-
     assert(next_tick >= curTick);
     return next_tick;
 }
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 13e545064..806c7ed85 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -115,11 +115,14 @@ void Bus::occupyBus(PacketPtr pkt)
     //Bring tickNextIdle up to the present tick
     //There is some potential ambiguity where a cycle starts, which might make
     //a difference when devices are acting right around a cycle boundary. Using
-    //a < allows things which happen exactly on a cycle boundary to take up only
-    //the following cycle. Anthing that happens later will have to "wait" for
-    //the end of that cycle, and then start using the bus after that.
-    while (tickNextIdle < curTick)
-        tickNextIdle += clock;
+    //a < allows things which happen exactly on a cycle boundary to take up
+    //only the following cycle. Anything that happens later will have to "wait"
+    //for the end of that cycle, and then start using the bus after that.
+    if (tickNextIdle < curTick) {
+        tickNextIdle = curTick;
+        if (tickNextIdle % clock != 0)
+            tickNextIdle -= (curTick % clock) + clock;
+    }
 
     // The packet will be sent. Figure out how long it occupies the bus, and
     // how much of that time is for the first "word", aka bus width.
@@ -132,10 +135,9 @@ void Bus::occupyBus(PacketPtr pkt)
         // We're using the "adding instead of dividing" trick again here
         if (pkt->hasData()) {
             int dataSize = pkt->getSize();
-            for (int transmitted = 0; transmitted < dataSize;
-                    transmitted += width) {
+            numCycles += dataSize/width;
+            if (dataSize % width)
                 numCycles++;
-            }
         } else {
             // If the packet didn't have data, it must have been a response.
             // Those use the bus for one cycle to send their data.