From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Tue, 15 Nov 2022 20:56:13 +0000 (+0300)
Subject: power_insn: switch to SVP64SubVL enum
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d55088fc261b33e628a00e320edc981833512f30;p=openpower-isa.git

power_insn: switch to SVP64SubVL enum
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index eaf89238..e62fda92 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -40,6 +40,7 @@ from openpower.decoder.power_enums import (
     SVExtraReg as _SVExtraReg,
     SVP64Predicate as _SVP64Predicate,
     SVP64PredicateType as _SVP64PredicateType,
+    SVP64SubVL as _SVP64SubVL,
 )
 from openpower.decoder.selectable_int import (
     SelectableInt as _SelectableInt,
@@ -2489,18 +2490,19 @@ class SpecifierWidth(Specifier):
 
 @_dataclasses.dataclass(eq=True, frozen=True)
 class SpecifierSubVL(Specifier):
-    value: int
+    value: _SVP64SubVL
 
     @classmethod
     def match(cls, desc, record):
-        value = {"vec2": 1, "vec3": 2, "vec4": 3}.get(desc)
-        if value is None:
+        try:
+            value = _SVP64SubVL(desc)
+        except ValueError:
             return None
 
         return cls(record=record, value=value)
 
     def assemble(self, insn):
-        insn.prefix.rm.subvl = self.value
+        insn.prefix.rm.subvl = int(self.value.value)
 
 
 @_dataclasses.dataclass(eq=True, frozen=True)