From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 18 Mar 2021 11:21:05 +0000 (+0000)
Subject: add option to create microwatt-formatted VHDL
X-Git-Tag: DRAFT_SVP64_0_1~1184
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d55ada3f6abeaf8203bc4317630ffd5d2822ccfa;p=libreriscv.git

add option to create microwatt-formatted VHDL
---

diff --git a/openpower/sv_analysis.py b/openpower/sv_analysis.py
index 5e47025b9..aa59afb3d 100644
--- a/openpower/sv_analysis.py
+++ b/openpower/sv_analysis.py
@@ -215,6 +215,7 @@ def process_csvs():
                 continue
             if insn_name.startswith('bc') or 'rfid' in insn_name:
                 continue
+
             insns[insn_name] = row # accumulate csv data by instruction
             insn_to_csv[insn_name] = csvname_ # CSV file name by instruction
             dkey = create_key(row)
@@ -571,8 +572,10 @@ def process_csvs():
         #csvcols = ['insn', 'Ptype', 'Etype', '0', '1', '2', '3']
         write_csv("%s.csv" % value, csv, csvcols)
 
+    # okaaay, now we re-read them back in for producing microwatt SV
+
     # get SVP64 augmented CSV files
-    svt = SVP64RM()
+    svt = SVP64RM(microwatt_format=True)
     # Expand that (all .csv files)
     pth = find_wiki_file("*.csv")