From: lkcl <lkcl@web>
Date: Sat, 11 Jun 2022 18:38:14 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1843
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d561a6ce540543e68d1c6a93e6371341f844e3e8;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index a9d4440f4..b6662c901 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -475,10 +475,15 @@ FP Add "single").  Element-width overrides it would seem to
 be unnecessary, under these circunstances.
 
 However, it is not possible for `fadds` to fit two elements into
-64-bit: bear in mind that the FP32 bits are spread out across a 64
+64-bit: that breaks the simplicity of SVP64.
+Bear in mind that the FP32 bits are spread out across a 64
 bit register in FP64 format.  The solution here was to consider the
 "s" at the end of each instruction
 to mean "half of the element's width". Thus, `sv.fadds/ew=32`
 actually stores an FP16 spread out across the 32 bits of an
 element, in FP32 format, where `sv.fadd/ew=32` stores a full
 FP32 result into the full 32 bits.
+
+Where this breaks down is when attempting to do half-width on
+BF16 or FP16 operations: there does not exist a BF8 or an IEE754 FP8
+format, so these should be avoided.