From: Jordan Justen Date: Thu, 24 Sep 2015 08:06:56 +0000 (-0700) Subject: i965/cs: Store compute invocation information in brw context X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d57a85f32b2242e19c2d20e91af0218d41e1e9fe;p=mesa.git i965/cs: Store compute invocation information in brw context We will need this in an atom to setup a surface to read the gl_NumWorkGroups values from. Signed-off-by: Jordan Justen Reviewed-by: Kristian Høgsberg --- diff --git a/src/mesa/drivers/dri/i965/brw_compute.c b/src/mesa/drivers/dri/i965/brw_compute.c index c392152e48d..505023d2851 100644 --- a/src/mesa/drivers/dri/i965/brw_compute.c +++ b/src/mesa/drivers/dri/i965/brw_compute.c @@ -36,27 +36,18 @@ static void -brw_emit_gpgpu_walker(struct brw_context *brw, - const void *compute_param, - bool indirect) +brw_emit_gpgpu_walker(struct brw_context *brw) { const struct brw_cs_prog_data *prog_data = brw->cs.prog_data; - const GLuint *num_groups; + const GLuint *num_groups = brw->compute.num_work_groups; uint32_t indirect_flag; - if (!indirect) { - num_groups = (const GLuint *)compute_param; + if (brw->compute.num_work_groups_bo == NULL) { indirect_flag = 0; } else { - GLintptr indirect_offset = (GLintptr)compute_param; - static const GLuint indirect_group_counts[3] = { 0, 0, 0 }; - num_groups = indirect_group_counts; - - struct gl_buffer_object *indirect_buffer = brw->ctx.DispatchIndirectBuffer; - drm_intel_bo *bo = intel_bufferobj_buffer(brw, - intel_buffer_object(indirect_buffer), - indirect_offset, 3 * sizeof(GLuint)); + GLintptr indirect_offset = brw->compute.num_work_groups_offset; + drm_intel_bo *bo = brw->compute.num_work_groups_bo; indirect_flag = GEN7_GPGPU_INDIRECT_PARAMETER_ENABLE; @@ -115,9 +106,7 @@ brw_emit_gpgpu_walker(struct brw_context *brw, static void -brw_dispatch_compute_common(struct gl_context *ctx, - const void *compute_param, - bool indirect) +brw_dispatch_compute_common(struct gl_context *ctx) { struct brw_context *brw = brw_context(ctx); int estimated_buffer_space_needed; @@ -151,7 +140,7 @@ brw_dispatch_compute_common(struct gl_context *ctx, brw->no_batch_wrap = true; brw_upload_compute_state(brw); - brw_emit_gpgpu_walker(brw, compute_param, indirect); + brw_emit_gpgpu_walker(brw); brw->no_batch_wrap = false; @@ -191,17 +180,30 @@ brw_dispatch_compute_common(struct gl_context *ctx, static void brw_dispatch_compute(struct gl_context *ctx, const GLuint *num_groups) { - brw_dispatch_compute_common(ctx, - num_groups, - false); + struct brw_context *brw = brw_context(ctx); + + brw->compute.num_work_groups_bo = NULL; + brw->compute.num_work_groups = num_groups; + + brw_dispatch_compute_common(ctx); } static void brw_dispatch_compute_indirect(struct gl_context *ctx, GLintptr indirect) { - brw_dispatch_compute_common(ctx, - (void *)indirect, - true); + struct brw_context *brw = brw_context(ctx); + static const GLuint indirect_group_counts[3] = { 0, 0, 0 }; + struct gl_buffer_object *indirect_buffer = ctx->DispatchIndirectBuffer; + drm_intel_bo *bo = + intel_bufferobj_buffer(brw, + intel_buffer_object(indirect_buffer), + indirect, 3 * sizeof(GLuint)); + + brw->compute.num_work_groups_bo = bo; + brw->compute.num_work_groups_offset = indirect; + brw->compute.num_work_groups = indirect_group_counts; + + brw_dispatch_compute_common(ctx); } void diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 27e80ea3bd6..a65cac10d98 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1251,6 +1251,17 @@ struct brw_context uint32_t draw_params_offset; } draw; + struct { + /** + * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is + * an indirect call, and num_work_groups_offset is valid. Otherwise, + * num_work_groups is set based on glDispatchCompute. + */ + drm_intel_bo *num_work_groups_bo; + GLintptr num_work_groups_offset; + const GLuint *num_work_groups; + } compute; + struct { struct brw_vertex_element inputs[VERT_ATTRIB_MAX]; struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX];