From: lkcl <lkcl@web>
Date: Sat, 29 Apr 2023 13:00:02 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d5aed1e5d4b45aa909d7aa78e6f50159b2f4ab61;p=libreriscv.git

---

diff --git a/openpower/sv/twin_butterfly.mdwn b/openpower/sv/twin_butterfly.mdwn
index 69fde8b5d..cf3d0e645 100644
--- a/openpower/sv/twin_butterfly.mdwn
+++ b/openpower/sv/twin_butterfly.mdwn
@@ -52,7 +52,7 @@ A-Form
 
 ```
     |0     |6     |11      |16     |21      |26    |31 |
-    | PO   |  RT  |   RA   |   RB  |   SH   |   XO |/  |
+    | PO   |  RT  |   RA   |   RB  |   SH   |   XO |Rc |
 
 ```
 
@@ -79,6 +79,15 @@ Pseudo-code:
     RS <- (res2 & m | smask2) + s64_2
 ```
 
+Note that if Rc=1 an Illegal Instruction is raised.
+Rc=1 is `RESERVED`
+
+Similar to `RTp`, this instruction produces an implicit result,
+`RS`, which under Scalar circumstances is defined as `RT+1`.
+For SVP64 if `RT` is a Vector, `RS` begins immediately after the
+Vector `RT` where the length of `RT` is set by `SVSTATE.MAXVL`
+(Max Vector Length).
+
 Special Registers Altered:
 
 ```
@@ -95,7 +104,7 @@ X-Form
 
 ```
     |0     |6     |11      |16     |21      |31 |
-    | PO   |  FRT |  FRA   |  FRB  |   XO   |/  |
+    | PO   |  FRT |  FRA   |  FRB  |   XO   |Rc |
 ```
 
 * fdmadds FRT,FRA,FRB (Rc=0)
@@ -108,6 +117,28 @@ Pseudo-code:
     FRT <- FPMUL32(FRA, sub)
 ```
 
+The Floating-Point operand in register FRT is added to the floating-point
+operand in register FRB and the result stored in FRS.
+
+Using the exact same operand input register values from FRT and FRB that
+were used to create FRS, the Floating-Point operand in register FRB
+is subtracted from the floating-point operand in register FRT and the
+result then multiplied by FRA to create an intermediate result that is
+stored in FRT.
+
+The subtraction and multiply are treated as if they were `fsub`
+followed by `fmul`, not `fmsub`.  The creation of FRS and FRT are
+treated as parallel independent operations.
+
+Note that if Rc=1 an Illegal Instruction is raised.
+Rc=1 is `RESERVED`
+
+Similar to `FRTp`, this instruction produces an implicit result,
+`FRS`, which under Scalar circumstances is defined as `FRT+1`.
+For SVP64 if `FRT` is a Vector, `FRS` begins immediately after the
+Vector `FRT` where the length of `FRT` is set by `SVSTATE.MAXVL`
+(Max Vector Length).
+
 Special Registers Altered:
 
 ```
@@ -124,7 +155,7 @@ X-Form
 
 ```
     |0     |6     |11      |16     |21      |31 |
-    | PO   |  FRT |  FRA   |  FRB  |   XO   |/  |
+    | PO   |  FRT |  FRA   |  FRB  |   XO   |Rc |
 ```
 
 * ffmadds FRT,FRA,FRB (Rc=0)
@@ -136,6 +167,44 @@ Pseudo-code:
     FRT <- FPMULADD32(FRT, FRA, FRB, 1, 1)
 ```
 
+The two operations
+
+```
+    FRS <- -([(FRT) * —(FRA)] - (FRB))
+    FRT <-   [(FRT) * —(FRA)] + (FRB)
+```
+
+are performed.
+
+The floating-point operand in register FRT is multiplied
+by the floating-point operand in register FRA. The float-
+ing-point operand in register FRB is added to
+this intermediate result, and the intermediate stored in FRS.
+
+Using the exact same values of FRT, FRT and FRB as used to create FRS,
+the floating-point operand in register FRT is multiplied
+by the floating-point operand in register FRA. The float-
+ing-point operand in register FRB is subtracted from
+this intermediate result, and the intermediate stored in FRT.
+
+FRT is created as if
+a `fmadds` operation had been performed. FRS is created as if
+a `fnmsubs` operation had simultaneously been performed with
+the exact same register operands, in parallel, independently,
+at exactly the same time.
+
+FRT is a Read-Modify-Write operation.  
+
+Note that if Rc=1 an Illegal Instruction is raised.
+Rc=1 is `RESERVED`
+
+Similar to `FRTp`, this instruction produces an implicit result,
+`FRS`, which under Scalar circumstances is defined as `FRT+1`.
+For SVP64 if `FRT` is a Vector, `FRS` begins immediately after the
+Vector `FRT` where the length of `FRT` is set by `SVSTATE.MAXVL`
+(Max Vector Length).
+
+
 Special Registers Altered:
 
 ```