From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Aug 2015 11:05:32 +0000 (+0200)
Subject: Added $tribuf and $_TBUF_ sim models
X-Git-Tag: yosys-0.6~188
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d5b1a90b33458616c9c002062330c5420335ed31;p=yosys.git

Added $tribuf and $_TBUF_ sim models
---

diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 9a820f71c..3b7d55c6e 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -132,6 +132,12 @@ output Y;
 assign Y = ~((A | B) & (C | D));
 endmodule
 
+module \$_TBUF_ (A, E, Y);
+input A, E;
+output Y;
+assign Y = E ? A : 1'bz;
+endmodule
+
 module  \$_SR_NN_ (S, R, Q);
 input S, R;
 output reg Q;
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 275c469b8..2a56b3a1e 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1156,6 +1156,20 @@ endmodule
 `endif
 // --------------------------------------------------------
 
+module \$tribuf (A, EN, Y);
+
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A;
+input EN;
+output [WIDTH-1:0] Y;
+
+assign Y = EN ? A : 'bz;
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$assert (A, EN);
 
 input A, EN;