From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sat, 14 May 2022 19:25:53 +0000 (+0000)
Subject: ppc-opc: support grev and grev. instructions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d5c4afca24ed58dbde8e6e4ed2c6adf511fdf63a;p=binutils-gdb.git

ppc-opc: support grev and grev. instructions
---

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index bb1a84b8d5d..429152d4006 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4701,6 +4701,13 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
    | (((uint64_t)(rc)) & 1))
 #define TLI_MASK	TLI (0x3f, 0x3, 1)
 
+/* An XBM5 form instruction. */
+#define XBM5(op, xop, rc)			\
+  (OP (op)					\
+   | ((((uint64_t)(xop)) & 0x3ff) << 1)		\
+   | (((uint64_t)(rc)) & 1))
+#define XBM5_MASK	XBM5 (0x3f, 0x3ff, 1)
+
 /* The BO encodings used in extended conditional branch mnemonics.  */
 #define BODNZF	(0x0)
 #define BODNZFP	(0x1)
@@ -5854,6 +5861,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"ternlogi",	TLI(5,0,0),	TLI_MASK,	DRAFT,	PPCVLE,	{RT, RA, RB, TLIf}},
 {"ternlogi.",	TLI(5,0,1),	TLI_MASK,	DRAFT,	PPCVLE,	{RT, RA, RB, TLIf}},
 
+{"grev",	XBM5(5,150,0),	XBM5_MASK,	DRAFT,	PPCVLE,	{RT, RA, RB}},
+{"grev.",	XBM5(5,150,1),	XBM5_MASK,	DRAFT,	PPCVLE,	{RT, RA, RB}},
+
 {"lxvp",	DQXP(6,0),	DQXP_MASK,   POWER10,	PPCVLE,		{XTP, DQ, RA0}},
 {"stxvp",	DQXP(6,1),	DQXP_MASK,   POWER10,	PPCVLE,		{XTP, DQ, RA0}},