From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 26 Jun 2020 17:58:28 +0000 (+0100)
Subject: clean up output from BareLoadStoreUnit
X-Git-Tag: div_pipeline~260
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d5cb8a7e3d782d40892bb996f1ffad4ef7abf023;p=soc.git

clean up output from BareLoadStoreUnit
---

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index c91769c9..ec80dd6d 100644
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -12,7 +12,9 @@ __all__ = ["LoadStoreUnitInterface", "BareLoadStoreUnit",
 
 class LoadStoreUnitInterface:
     def __init__(self, addr_wid=32, mask_wid=4, data_wid=32):
+        print ("loadstoreunit addr mask data", addr_wid, mask_wid, data_wid)
         self.dbus = Record(make_wb_layout(addr_wid, mask_wid, data_wid))
+        print (self.dbus.sel.shape())
         self.mask_wid = mask_wid
         self.addr_wid = addr_wid
         self.data_wid = data_wid
@@ -70,6 +72,14 @@ class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
                 self.dbus.we.eq(self.x_st_i),
                 self.dbus.dat_w.eq(self.x_st_data_i)
             ]
+        with m.Else():
+            m.d.sync += [
+                self.dbus.adr.eq(0),
+                self.dbus.sel.eq(0),
+                self.dbus.we.eq(0),
+                self.dbus.sel.eq(0),
+                self.dbus.dat_w.eq(0),
+            ]
 
         with m.If(self.dbus.cyc & self.dbus.err):
             m.d.sync += [