From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 8 Jun 2019 00:00:36 +0000 (-0700)
Subject: Update CHANGELOG
X-Git-Tag: working-ls180~1208^2~177
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d5f0b73fd9ff3a5d015faf566adcebdc29bab2b2;p=yosys.git

Update CHANGELOG
---

diff --git a/CHANGELOG b/CHANGELOG
index 149443c74..c1b548aeb 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -16,12 +16,10 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
-<<<<<<< HEAD
-    - Added "muxpack" pass
-=======
     - Added "read_aiger" frontend
->>>>>>> origin/master
+    - Added "muxpack" pass
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
+    - "synth_xilinx" to now infer wide multiplexers
 
 
 Yosys 0.7 .. Yosys 0.8