From: lkcl <lkcl@web>
Date: Fri, 7 Jul 2023 05:05:27 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d5f13b1757f1708ca410a193ac0f3f2d69080210;p=libreriscv.git

---

diff --git a/HDL_workflow/HyperRAM.mdwn b/HDL_workflow/HyperRAM.mdwn
index 93b6b1e10..9e0670b3d 100644
--- a/HDL_workflow/HyperRAM.mdwn
+++ b/HDL_workflow/HyperRAM.mdwn
@@ -9,7 +9,6 @@
   <https://ftp.libre-soc.org/W956x8MBYA_64Mb_HyperBus_pSRAM_TFBGA24_datasheet_A01-005_20211208.pdf>
 * Winbond Verilog Model for W956A8MBY:
   <https://www.winbond.com/resource-files/W956x8MBY_verilog_p.zip>
-* VHDL hyperram <https://github.com/MJoergen/HyperRAM>
 
 ```
 from nmigen.resources.memory import HyperRAMResources