From: lkcl <lkcl@web>
Date: Sat, 18 Sep 2021 11:25:07 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~76
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d5f41fe7e286641134fefef26dffef5810440d16;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index e5e077015..5cad7b59c 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -187,7 +187,9 @@ Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or in
 Mode is an augmentation of SV behaviour.  Different types of
 instructions have different needs, similar to Power ISA 
 v3.1 64 bit prefix 8LS and MTRR formats apply to different
-instruction types
+instruction types.  Modes include Reduction, Iteration, arithmetic
+saturation, and Fail-First.  More specific details in each
+section and in the [[svp64/appendix]]
 
 * For condition register operations see [[sv/cr_ops]]
 * For LD/ST Modes, see [[sv/ldst]].