From: Cole Poirier <colepoirier@gmail.com>
Date: Wed, 4 Nov 2020 00:55:59 +0000 (-0800)
Subject: update photo for stlinkv2 JTAG wires in HDL_Workflow/ECP5_FPGA
X-Git-Tag: convert-csv-opcode-to-binary~1875
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d5f65e25cdae7d55b415507a41a508e284441baf;p=libreriscv.git

update photo for stlinkv2 JTAG wires in HDL_Workflow/ECP5_FPGA
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diff --git a/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg b/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg
index d56adc850..c03ef96ee 100644
Binary files a/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg and b/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg differ