From: H.J. Lu Date: Mon, 17 Sep 2018 16:31:07 +0000 (-0700) Subject: x86: Set Vex=1 on VEX.128 only vmovd and vmovq X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d5f787c2bc90793c1d781b7291758e77067daad5;p=binutils-gdb.git x86: Set Vex=1 on VEX.128 only vmovd and vmovq AVX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64" and "VMOVD r64/m64, xmm2" can only be encoded with VEX.128. Set Vex=1 on VEX.128 only vmovd and vmovq. gas/ PR gas/23665 * testsuite/gas/i386/avx-scalar.s: Remove vmovq and vmovd tests. * testsuite/gas/i386/x86-64-avx-scalar.s: Likewise. * testsuite/gas/i386/avx-scalar-intel.d: Updated. * testsuite/gas/i386/avx-scalar.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. * testsuite/gas/i386/i386.exp: Run avx-scalar2 and x86-64-avx-scalar2. * testsuite/gas/i386/avx-scalar-2.d: New file. * testsuite/gas/i386/avx-scalar-2.s: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.s: Likewise. opcodes/ PR gas/23665 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and VEX_LEN_0F7E_P_2 entries. * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq. * i386-tbl.h: Regenerated. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 7428c24526b..4ea1d1c694c 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,19 @@ +2018-09-17 H.J. Lu + + PR gas/23665 + * testsuite/gas/i386/avx-scalar.s: Remove vmovq and vmovd tests. + * testsuite/gas/i386/x86-64-avx-scalar.s: Likewise. + * testsuite/gas/i386/avx-scalar-intel.d: Updated. + * testsuite/gas/i386/avx-scalar.d: Likewise. + * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. + * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. + * testsuite/gas/i386/i386.exp: Run avx-scalar2 and + x86-64-avx-scalar2. + * testsuite/gas/i386/avx-scalar-2.d: New file. + * testsuite/gas/i386/avx-scalar-2.s: Likewise. + * testsuite/gas/i386/x86-64-avx-scalar-2.d: Likewise. + * testsuite/gas/i386/x86-64-avx-scalar-2.s: Likewise. + 2018-09-17 H.J. Lu * gas/NEWS: Mention -mvexwig=[0|1] option. diff --git a/gas/testsuite/gas/i386/avx-scalar-2.d b/gas/testsuite/gas/i386/avx-scalar-2.d new file mode 100644 index 00000000000..15a5230cbfe --- /dev/null +++ b/gas/testsuite/gas/i386/avx-scalar-2.d @@ -0,0 +1,24 @@ +#as: -mavxscalar=256 -msse2avx +#objdump: -dw +#name: i386 VEX.128 scalar insns with -mavxscalar=256 -msse2avx + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: + +[a-f0-9]+: c5 f9 7e 21 vmovd %xmm4,\(%ecx\) + +[a-f0-9]+: c5 f9 7e e1 vmovd %xmm4,%ecx + +[a-f0-9]+: c5 f9 6e 21 vmovd \(%ecx\),%xmm4 + +[a-f0-9]+: c5 f9 6e e1 vmovd %ecx,%xmm4 + +[a-f0-9]+: c5 f9 7e 21 vmovd %xmm4,\(%ecx\) + +[a-f0-9]+: c5 f9 7e e1 vmovd %xmm4,%ecx + +[a-f0-9]+: c5 f9 6e 21 vmovd \(%ecx\),%xmm4 + +[a-f0-9]+: c5 f9 6e e1 vmovd %ecx,%xmm4 + +[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%ecx\) + +[a-f0-9]+: c5 fa 7e 21 vmovq \(%ecx\),%xmm4 + +[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%ecx\) + +[a-f0-9]+: c5 fa 7e 21 vmovq \(%ecx\),%xmm4 + +[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6 +#pass diff --git a/gas/testsuite/gas/i386/avx-scalar-2.s b/gas/testsuite/gas/i386/avx-scalar-2.s new file mode 100644 index 00000000000..f48347f412e --- /dev/null +++ b/gas/testsuite/gas/i386/avx-scalar-2.s @@ -0,0 +1,22 @@ +# Check VEX.128 scalar instructions with -mavxscalar=256 -msse2avx + + .allow_index_reg + .text +_start: + + movd %xmm4,(%ecx) + movd %xmm4,%ecx + movd (%ecx),%xmm4 + movd %ecx,%xmm4 + + vmovd %xmm4,(%ecx) + vmovd %xmm4,%ecx + vmovd (%ecx),%xmm4 + vmovd %ecx,%xmm4 + + movq %xmm4,(%ecx) + movq (%ecx),%xmm4 + vmovq %xmm4,(%ecx) + vmovq (%ecx),%xmm4 + + vmovq %xmm4,%xmm6 diff --git a/gas/testsuite/gas/i386/avx-scalar-intel.d b/gas/testsuite/gas/i386/avx-scalar-intel.d index b02ea19dd55..b928676b324 100644 --- a/gas/testsuite/gas/i386/avx-scalar-intel.d +++ b/gas/testsuite/gas/i386/avx-scalar-intel.d @@ -15,8 +15,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 fd 2e 21 vucomisd xmm4,QWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 ff 10 21 vmovsd xmm4,QWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 ff 11 21 vmovsd QWORD PTR \[ecx\],xmm4 -[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq QWORD PTR \[ecx\],xmm4 -[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq xmm4,QWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 ff 2d cc vcvtsd2si ecx,xmm4 [ ]*[a-f0-9]+: c5 ff 2d 09 vcvtsd2si ecx,QWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 ff 2c cc vcvttsd2si ecx,xmm4 @@ -195,10 +193,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 fc 2e 21 vucomiss xmm4,DWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 fe 10 21 vmovss xmm4,DWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 fe 11 21 vmovss DWORD PTR \[ecx\],xmm4 -[ ]*[a-f0-9]+: c5 fd 7e e1 vmovd ecx,xmm4 -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd DWORD PTR \[ecx\],xmm4 -[ ]*[a-f0-9]+: c5 fd 6e e1 vmovd xmm4,ecx -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd xmm4,DWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 fe 2d cc vcvtss2si ecx,xmm4 [ ]*[a-f0-9]+: c5 fe 2d 09 vcvtss2si ecx,DWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 fe 2c cc vcvttss2si ecx,xmm4 @@ -211,30 +205,18 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ce c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[ecx\] [ ]*[a-f0-9]+: c4 e3 4d 0a d4 07 vroundss xmm2,xmm6,xmm4,0x7 [ ]*[a-f0-9]+: c4 e3 4d 0a 11 07 vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x7 -[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4 [ ]*[a-f0-9]+: c5 cf 10 d4 vmovsd xmm2,xmm6,xmm4 [ ]*[a-f0-9]+: c5 ce 10 d4 vmovss xmm2,xmm6,xmm4 -[ ]*[a-f0-9]+: c5 fd 7e 05 34 12 00 00 vmovd DWORD PTR ds:0x1234,xmm0 [ ]*[a-f0-9]+: c5 ff 2a 3d 34 12 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR ds:0x1234 -[ ]*[a-f0-9]+: c5 fd 7e 45 00 vmovd DWORD PTR \[ebp\+0x0\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a 7d 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+0x0\] -[ ]*[a-f0-9]+: c5 fd 7e 04 24 vmovd DWORD PTR \[esp\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a 3c 24 vcvtsi2sd xmm7,xmm0,DWORD PTR \[esp\] -[ ]*[a-f0-9]+: c5 fd 7e 85 99 00 00 00 vmovd DWORD PTR \[ebp\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a bd 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 04 25 99 00 00 00 vmovd DWORD PTR \[eiz\*1\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a 3c 25 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eiz\*1\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 04 65 99 00 00 00 vmovd DWORD PTR \[eiz\*2\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a 3c 65 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eiz\*2\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 84 20 99 00 00 00 vmovd DWORD PTR \[eax\+eiz\*1\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a bc 20 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+eiz\*1\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 84 60 99 00 00 00 vmovd DWORD PTR \[eax\+eiz\*2\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a bc 60 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+eiz\*2\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 84 98 99 00 00 00 vmovd DWORD PTR \[eax\+ebx\*4\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a bc 98 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+ebx\*4\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 84 cc 99 00 00 00 vmovd DWORD PTR \[esp\+ecx\*8\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a bc cc 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[esp\+ecx\*8\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 84 15 99 00 00 00 vmovd DWORD PTR \[ebp\+edx\*1\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a bc 15 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+edx\*1\+0x99\] [ ]*[a-f0-9]+: c5 fd 2f f4 vcomisd xmm6,xmm4 [ ]*[a-f0-9]+: c5 fd 2f 21 vcomisd xmm4,QWORD PTR \[ecx\] @@ -246,10 +228,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ff 10 21 vmovsd xmm4,QWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 ff 11 21 vmovsd QWORD PTR \[ecx\],xmm4 [ ]*[a-f0-9]+: c5 ff 11 21 vmovsd QWORD PTR \[ecx\],xmm4 -[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq QWORD PTR \[ecx\],xmm4 -[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq xmm4,QWORD PTR \[ecx\] -[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq QWORD PTR \[ecx\],xmm4 -[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq xmm4,QWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 ff 2d cc vcvtsd2si ecx,xmm4 [ ]*[a-f0-9]+: c5 ff 2d 09 vcvtsd2si ecx,QWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 ff 2d 09 vcvtsd2si ecx,QWORD PTR \[ecx\] @@ -518,12 +496,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 fe 10 21 vmovss xmm4,DWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 fe 11 21 vmovss DWORD PTR \[ecx\],xmm4 [ ]*[a-f0-9]+: c5 fe 11 21 vmovss DWORD PTR \[ecx\],xmm4 -[ ]*[a-f0-9]+: c5 fd 7e e1 vmovd ecx,xmm4 -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd DWORD PTR \[ecx\],xmm4 -[ ]*[a-f0-9]+: c5 fd 6e e1 vmovd xmm4,ecx -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd xmm4,DWORD PTR \[ecx\] -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd DWORD PTR \[ecx\],xmm4 -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd xmm4,DWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 fe 2d cc vcvtss2si ecx,xmm4 [ ]*[a-f0-9]+: c5 fe 2d 09 vcvtss2si ecx,DWORD PTR \[ecx\] [ ]*[a-f0-9]+: c5 fe 2d 09 vcvtss2si ecx,DWORD PTR \[ecx\] @@ -542,27 +514,16 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c4 e3 4d 0a d4 07 vroundss xmm2,xmm6,xmm4,0x7 [ ]*[a-f0-9]+: c4 e3 4d 0a 11 07 vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x7 [ ]*[a-f0-9]+: c4 e3 4d 0a 11 07 vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x7 -[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4 [ ]*[a-f0-9]+: c5 cf 10 d4 vmovsd xmm2,xmm6,xmm4 [ ]*[a-f0-9]+: c5 ce 10 d4 vmovss xmm2,xmm6,xmm4 -[ ]*[a-f0-9]+: c5 fd 7e 05 34 12 00 00 vmovd DWORD PTR ds:0x1234,xmm0 [ ]*[a-f0-9]+: c5 ff 2a 3d 34 12 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR ds:0x1234 -[ ]*[a-f0-9]+: c5 fd 7e 45 00 vmovd DWORD PTR \[ebp\+0x0\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a 7d 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+0x0\] -[ ]*[a-f0-9]+: c5 fd 7e 85 99 00 00 00 vmovd DWORD PTR \[ebp\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a bd 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 04 25 99 00 00 00 vmovd DWORD PTR \[eiz\*1\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a 3c 25 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eiz\*1\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 04 65 99 00 00 00 vmovd DWORD PTR \[eiz\*2\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a 3c 65 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eiz\*2\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 84 20 99 00 00 00 vmovd DWORD PTR \[eax\+eiz\*1\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a bc 20 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+eiz\*1\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 84 60 99 00 00 00 vmovd DWORD PTR \[eax\+eiz\*2\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a bc 60 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+eiz\*2\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 84 98 99 00 00 00 vmovd DWORD PTR \[eax\+ebx\*4\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a bc 98 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+ebx\*4\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 84 cc 99 00 00 00 vmovd DWORD PTR \[esp\+ecx\*8\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a bc cc 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[esp\+ecx\*8\+0x99\] -[ ]*[a-f0-9]+: c5 fd 7e 84 15 99 00 00 00 vmovd DWORD PTR \[ebp\+edx\*1\+0x99\],xmm0 [ ]*[a-f0-9]+: c5 ff 2a bc 15 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+edx\*1\+0x99\] #pass diff --git a/gas/testsuite/gas/i386/avx-scalar.d b/gas/testsuite/gas/i386/avx-scalar.d index 0d20bd56e3c..47bb3ed963f 100644 --- a/gas/testsuite/gas/i386/avx-scalar.d +++ b/gas/testsuite/gas/i386/avx-scalar.d @@ -14,8 +14,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 fd 2e 21 vucomisd \(%ecx\),%xmm4 [ ]*[a-f0-9]+: c5 ff 10 21 vmovsd \(%ecx\),%xmm4 [ ]*[a-f0-9]+: c5 ff 11 21 vmovsd %xmm4,\(%ecx\) -[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%ecx\) -[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%ecx\),%xmm4 [ ]*[a-f0-9]+: c5 ff 2d cc vcvtsd2si %xmm4,%ecx [ ]*[a-f0-9]+: c5 ff 2d 09 vcvtsd2si \(%ecx\),%ecx [ ]*[a-f0-9]+: c5 ff 2c cc vcvttsd2si %xmm4,%ecx @@ -194,10 +192,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 fc 2e 21 vucomiss \(%ecx\),%xmm4 [ ]*[a-f0-9]+: c5 fe 10 21 vmovss \(%ecx\),%xmm4 [ ]*[a-f0-9]+: c5 fe 11 21 vmovss %xmm4,\(%ecx\) -[ ]*[a-f0-9]+: c5 fd 7e e1 vmovd %xmm4,%ecx -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd %xmm4,\(%ecx\) -[ ]*[a-f0-9]+: c5 fd 6e e1 vmovd %ecx,%xmm4 -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd \(%ecx\),%xmm4 [ ]*[a-f0-9]+: c5 fe 2d cc vcvtss2si %xmm4,%ecx [ ]*[a-f0-9]+: c5 fe 2d 09 vcvtss2si \(%ecx\),%ecx [ ]*[a-f0-9]+: c5 fe 2c cc vcvttss2si %xmm4,%ecx @@ -210,30 +204,18 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ce c2 11 07 vcmpordss \(%ecx\),%xmm6,%xmm2 [ ]*[a-f0-9]+: c4 e3 4d 0a d4 07 vroundss \$0x7,%xmm4,%xmm6,%xmm2 [ ]*[a-f0-9]+: c4 e3 4d 0a 11 07 vroundss \$0x7,\(%ecx\),%xmm6,%xmm2 -[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6 [ ]*[a-f0-9]+: c5 cf 10 d4 vmovsd %xmm4,%xmm6,%xmm2 [ ]*[a-f0-9]+: c5 ce 10 d4 vmovss %xmm4,%xmm6,%xmm2 -[ ]*[a-f0-9]+: c5 fd 7e 05 34 12 00 00 vmovd %xmm0,0x1234 [ ]*[a-f0-9]+: c5 ff 2a 3d 34 12 00 00 vcvtsi2sdl 0x1234,%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 45 00 vmovd %xmm0,0x0\(%ebp\) [ ]*[a-f0-9]+: c5 ff 2a 7d 00 vcvtsi2sdl 0x0\(%ebp\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 04 24 vmovd %xmm0,\(%esp\) [ ]*[a-f0-9]+: c5 ff 2a 3c 24 vcvtsi2sdl \(%esp\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 85 99 00 00 00 vmovd %xmm0,0x99\(%ebp\) [ ]*[a-f0-9]+: c5 ff 2a bd 99 00 00 00 vcvtsi2sdl 0x99\(%ebp\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 04 25 99 00 00 00 vmovd %xmm0,0x99\(,%eiz,1\) [ ]*[a-f0-9]+: c5 ff 2a 3c 25 99 00 00 00 vcvtsi2sdl 0x99\(,%eiz,1\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 04 65 99 00 00 00 vmovd %xmm0,0x99\(,%eiz,2\) [ ]*[a-f0-9]+: c5 ff 2a 3c 65 99 00 00 00 vcvtsi2sdl 0x99\(,%eiz,2\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 84 20 99 00 00 00 vmovd %xmm0,0x99\(%eax,%eiz,1\) [ ]*[a-f0-9]+: c5 ff 2a bc 20 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%eiz,1\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 84 60 99 00 00 00 vmovd %xmm0,0x99\(%eax,%eiz,2\) [ ]*[a-f0-9]+: c5 ff 2a bc 60 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%eiz,2\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 84 98 99 00 00 00 vmovd %xmm0,0x99\(%eax,%ebx,4\) [ ]*[a-f0-9]+: c5 ff 2a bc 98 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%ebx,4\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 84 cc 99 00 00 00 vmovd %xmm0,0x99\(%esp,%ecx,8\) [ ]*[a-f0-9]+: c5 ff 2a bc cc 99 00 00 00 vcvtsi2sdl 0x99\(%esp,%ecx,8\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 84 15 99 00 00 00 vmovd %xmm0,0x99\(%ebp,%edx,1\) [ ]*[a-f0-9]+: c5 ff 2a bc 15 99 00 00 00 vcvtsi2sdl 0x99\(%ebp,%edx,1\),%xmm0,%xmm7 [ ]*[a-f0-9]+: c5 fd 2f f4 vcomisd %xmm4,%xmm6 [ ]*[a-f0-9]+: c5 fd 2f 21 vcomisd \(%ecx\),%xmm4 @@ -245,10 +227,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ff 10 21 vmovsd \(%ecx\),%xmm4 [ ]*[a-f0-9]+: c5 ff 11 21 vmovsd %xmm4,\(%ecx\) [ ]*[a-f0-9]+: c5 ff 11 21 vmovsd %xmm4,\(%ecx\) -[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%ecx\) -[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%ecx\),%xmm4 -[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%ecx\) -[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%ecx\),%xmm4 [ ]*[a-f0-9]+: c5 ff 2d cc vcvtsd2si %xmm4,%ecx [ ]*[a-f0-9]+: c5 ff 2d 09 vcvtsd2si \(%ecx\),%ecx [ ]*[a-f0-9]+: c5 ff 2d 09 vcvtsd2si \(%ecx\),%ecx @@ -517,12 +495,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 fe 10 21 vmovss \(%ecx\),%xmm4 [ ]*[a-f0-9]+: c5 fe 11 21 vmovss %xmm4,\(%ecx\) [ ]*[a-f0-9]+: c5 fe 11 21 vmovss %xmm4,\(%ecx\) -[ ]*[a-f0-9]+: c5 fd 7e e1 vmovd %xmm4,%ecx -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd %xmm4,\(%ecx\) -[ ]*[a-f0-9]+: c5 fd 6e e1 vmovd %ecx,%xmm4 -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd \(%ecx\),%xmm4 -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd %xmm4,\(%ecx\) -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd \(%ecx\),%xmm4 [ ]*[a-f0-9]+: c5 fe 2d cc vcvtss2si %xmm4,%ecx [ ]*[a-f0-9]+: c5 fe 2d 09 vcvtss2si \(%ecx\),%ecx [ ]*[a-f0-9]+: c5 fe 2d 09 vcvtss2si \(%ecx\),%ecx @@ -541,27 +513,16 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c4 e3 4d 0a d4 07 vroundss \$0x7,%xmm4,%xmm6,%xmm2 [ ]*[a-f0-9]+: c4 e3 4d 0a 11 07 vroundss \$0x7,\(%ecx\),%xmm6,%xmm2 [ ]*[a-f0-9]+: c4 e3 4d 0a 11 07 vroundss \$0x7,\(%ecx\),%xmm6,%xmm2 -[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6 [ ]*[a-f0-9]+: c5 cf 10 d4 vmovsd %xmm4,%xmm6,%xmm2 [ ]*[a-f0-9]+: c5 ce 10 d4 vmovss %xmm4,%xmm6,%xmm2 -[ ]*[a-f0-9]+: c5 fd 7e 05 34 12 00 00 vmovd %xmm0,0x1234 [ ]*[a-f0-9]+: c5 ff 2a 3d 34 12 00 00 vcvtsi2sdl 0x1234,%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 45 00 vmovd %xmm0,0x0\(%ebp\) [ ]*[a-f0-9]+: c5 ff 2a 7d 00 vcvtsi2sdl 0x0\(%ebp\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 85 99 00 00 00 vmovd %xmm0,0x99\(%ebp\) [ ]*[a-f0-9]+: c5 ff 2a bd 99 00 00 00 vcvtsi2sdl 0x99\(%ebp\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 04 25 99 00 00 00 vmovd %xmm0,0x99\(,%eiz,1\) [ ]*[a-f0-9]+: c5 ff 2a 3c 25 99 00 00 00 vcvtsi2sdl 0x99\(,%eiz,1\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 04 65 99 00 00 00 vmovd %xmm0,0x99\(,%eiz,2\) [ ]*[a-f0-9]+: c5 ff 2a 3c 65 99 00 00 00 vcvtsi2sdl 0x99\(,%eiz,2\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 84 20 99 00 00 00 vmovd %xmm0,0x99\(%eax,%eiz,1\) [ ]*[a-f0-9]+: c5 ff 2a bc 20 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%eiz,1\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 84 60 99 00 00 00 vmovd %xmm0,0x99\(%eax,%eiz,2\) [ ]*[a-f0-9]+: c5 ff 2a bc 60 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%eiz,2\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 84 98 99 00 00 00 vmovd %xmm0,0x99\(%eax,%ebx,4\) [ ]*[a-f0-9]+: c5 ff 2a bc 98 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%ebx,4\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 84 cc 99 00 00 00 vmovd %xmm0,0x99\(%esp,%ecx,8\) [ ]*[a-f0-9]+: c5 ff 2a bc cc 99 00 00 00 vcvtsi2sdl 0x99\(%esp,%ecx,8\),%xmm0,%xmm7 -[ ]*[a-f0-9]+: c5 fd 7e 84 15 99 00 00 00 vmovd %xmm0,0x99\(%ebp,%edx,1\) [ ]*[a-f0-9]+: c5 ff 2a bc 15 99 00 00 00 vcvtsi2sdl 0x99\(%ebp,%edx,1\),%xmm0,%xmm7 #pass diff --git a/gas/testsuite/gas/i386/avx-scalar.s b/gas/testsuite/gas/i386/avx-scalar.s index fbda32e0754..152fe0034eb 100644 --- a/gas/testsuite/gas/i386/avx-scalar.s +++ b/gas/testsuite/gas/i386/avx-scalar.s @@ -16,11 +16,6 @@ _start: # Tests for op xmm, mem64 vmovsd %xmm4,(%ecx) -# Tests for op xmm, regq/mem64 -# Tests for op regq/mem64, xmm - vmovq %xmm4,(%ecx) - vmovq (%ecx),%xmm4 - # Tests for op xmm/mem64, regl vcvtsd2si %xmm4,%ecx vcvtsd2si (%ecx),%ecx @@ -213,13 +208,6 @@ _start: # Tests for op xmm, mem32 vmovss %xmm4,(%ecx) -# Tests for op xmm, regl/mem32 -# Tests for op regl/mem32, xmm - vmovd %xmm4,%ecx - vmovd %xmm4,(%ecx) - vmovd %ecx,%xmm4 - vmovd (%ecx),%xmm4 - # Tests for op xmm/mem32, regl vcvtss2si %xmm4,%ecx vcvtss2si (%ecx),%ecx @@ -238,35 +226,21 @@ _start: vroundss $7,%xmm4,%xmm6,%xmm2 vroundss $7,(%ecx),%xmm6,%xmm2 -# Tests for op xmm, xmm - vmovq %xmm4,%xmm6 - # Tests for op xmm, xmm, xmm vmovsd %xmm4,%xmm6,%xmm2 vmovss %xmm4,%xmm6,%xmm2 #Tests with different memory and register operands. - vmovd %xmm0,0x1234 vcvtsi2sdl 0x1234,%xmm0,%xmm7 - vmovd %xmm0,(%ebp) vcvtsi2sdl (%ebp),%xmm0,%xmm7 - vmovd %xmm0,(%esp) vcvtsi2sdl (%esp),%xmm0,%xmm7 - vmovd %xmm0,0x99(%ebp) vcvtsi2sdl 0x99(%ebp),%xmm0,%xmm7 - vmovd %xmm0,0x99(,%eiz) vcvtsi2sdl 0x99(,%eiz),%xmm0,%xmm7 - vmovd %xmm0,0x99(,%eiz,2) vcvtsi2sdl 0x99(,%eiz,2),%xmm0,%xmm7 - vmovd %xmm0,0x99(%eax,%eiz) vcvtsi2sdl 0x99(%eax,%eiz),%xmm0,%xmm7 - vmovd %xmm0,0x99(%eax,%eiz,2) vcvtsi2sdl 0x99(%eax,%eiz,2),%xmm0,%xmm7 - vmovd %xmm0,0x99(%eax,%ebx,4) vcvtsi2sdl 0x99(%eax,%ebx,4),%xmm0,%xmm7 - vmovd %xmm0,0x99(%esp,%ecx,8) vcvtsi2sdl 0x99(%esp,%ecx,8),%xmm0,%xmm7 - vmovd %xmm0,0x99(%ebp,%edx,1) vcvtsi2sdl 0x99(%ebp,%edx,1),%xmm0,%xmm7 .intel_syntax noprefix @@ -287,13 +261,6 @@ _start: vmovsd QWORD PTR [ecx],xmm4 vmovsd [ecx],xmm4 -# Tests for op xmm, regq/mem64 -# Tests for op regq/mem64, xmm - vmovq QWORD PTR [ecx],xmm4 - vmovq xmm4,QWORD PTR [ecx] - vmovq [ecx],xmm4 - vmovq xmm4,[ecx] - # Tests for op xmm/mem64, regl vcvtsd2si ecx,xmm4 vcvtsd2si ecx,QWORD PTR [ecx] @@ -576,15 +543,6 @@ _start: vmovss DWORD PTR [ecx],xmm4 vmovss [ecx],xmm4 -# Tests for op xmm, regl/mem32 -# Tests for op regl/mem32, xmm - vmovd ecx,xmm4 - vmovd DWORD PTR [ecx],xmm4 - vmovd xmm4,ecx - vmovd xmm4,DWORD PTR [ecx] - vmovd [ecx],xmm4 - vmovd xmm4,[ecx] - # Tests for op xmm/mem32, regl vcvtss2si ecx,xmm4 vcvtss2si ecx,DWORD PTR [ecx] @@ -609,31 +567,18 @@ _start: vroundss xmm2,xmm6,DWORD PTR [ecx],7 vroundss xmm2,xmm6,[ecx],7 -# Tests for op xmm, xmm - vmovq xmm6,xmm4 - # Tests for op xmm, xmm, xmm vmovsd xmm2,xmm6,xmm4 vmovss xmm2,xmm6,xmm4 #Tests with different memory and register operands. - vmovd DWORD PTR ds:0x1234,xmm0 vcvtsi2sd xmm7,xmm0,DWORD PTR ds:0x1234 - vmovd DWORD PTR [ebp],xmm0 vcvtsi2sd xmm7,xmm0,DWORD PTR [ebp] - vmovd DWORD PTR [ebp+0x99],xmm0 vcvtsi2sd xmm7,xmm0,DWORD PTR [ebp+0x99] - vmovd DWORD PTR [eiz*1+0x99],xmm0 vcvtsi2sd xmm7,xmm0,DWORD PTR [eiz*1+0x99] - vmovd DWORD PTR [eiz*2+0x99],xmm0 vcvtsi2sd xmm7,xmm0,DWORD PTR [eiz*2+0x99] - vmovd DWORD PTR [eax+eiz*1+0x99],xmm0 vcvtsi2sd xmm7,xmm0,DWORD PTR [eax+eiz*1+0x99] - vmovd DWORD PTR [eax+eiz*2+0x99],xmm0 vcvtsi2sd xmm7,xmm0,DWORD PTR [eax+eiz*2+0x99] - vmovd DWORD PTR [eax+ebx*4+0x99],xmm0 vcvtsi2sd xmm7,xmm0,DWORD PTR [eax+ebx*4+0x99] - vmovd DWORD PTR [esp+ecx*8+0x99],xmm0 vcvtsi2sd xmm7,xmm0,DWORD PTR [esp+ecx*8+0x99] - vmovd DWORD PTR [ebp+edx*1+0x99],xmm0 vcvtsi2sd xmm7,xmm0,DWORD PTR [ebp+edx*1+0x99] diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 90da612f5f8..150a0be1c18 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -207,6 +207,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "avx-intel" run_dump_test "avx-scalar" run_dump_test "avx-scalar-intel" + run_dump_test "avx-scalar-2" run_dump_test "avx256int" run_dump_test "avx256int-intel" run_dump_test "avx2" @@ -726,6 +727,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-avx-intel" run_dump_test "x86-64-avx-scalar" run_dump_test "x86-64-avx-scalar-intel" + run_dump_test "x86-64-avx-scalar-2" run_dump_test "x86-64-avx256int" run_dump_test "x86-64-avx_gfni" run_dump_test "x86-64-avx_gfni-intel" diff --git a/gas/testsuite/gas/i386/x86-64-avx-scalar-2.d b/gas/testsuite/gas/i386/x86-64-avx-scalar-2.d new file mode 100644 index 00000000000..037273ff62d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-scalar-2.d @@ -0,0 +1,32 @@ +#as: -mavxscalar=256 -msse2avx +#objdump: -dw +#name: x86-64 VEX.128 scalar insns with -mavxscalar=256 -msse2avx + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: + +[a-f0-9]+: c5 f9 7e 21 vmovd %xmm4,\(%rcx\) + +[a-f0-9]+: c5 f9 7e e1 vmovd %xmm4,%ecx + +[a-f0-9]+: c5 f9 6e 21 vmovd \(%rcx\),%xmm4 + +[a-f0-9]+: c5 f9 6e e1 vmovd %ecx,%xmm4 + +[a-f0-9]+: c4 e1 f9 6e e1 vmovq %rcx,%xmm4 + +[a-f0-9]+: c4 e1 f9 7e e1 vmovq %xmm4,%rcx + +[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%rcx\) + +[a-f0-9]+: c4 e1 f9 7e e1 vmovq %xmm4,%rcx + +[a-f0-9]+: c5 fa 7e 21 vmovq \(%rcx\),%xmm4 + +[a-f0-9]+: c4 e1 f9 6e e1 vmovq %rcx,%xmm4 + +[a-f0-9]+: c5 f9 7e 21 vmovd %xmm4,\(%rcx\) + +[a-f0-9]+: c5 f9 7e e1 vmovd %xmm4,%ecx + +[a-f0-9]+: c5 f9 6e 21 vmovd \(%rcx\),%xmm4 + +[a-f0-9]+: c5 f9 6e e1 vmovd %ecx,%xmm4 + +[a-f0-9]+: c4 e1 f9 7e e1 vmovq %xmm4,%rcx + +[a-f0-9]+: c4 e1 f9 6e e1 vmovq %rcx,%xmm4 + +[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%rcx\) + +[a-f0-9]+: c4 e1 f9 7e e1 vmovq %xmm4,%rcx + +[a-f0-9]+: c5 fa 7e 21 vmovq \(%rcx\),%xmm4 + +[a-f0-9]+: c4 e1 f9 6e e1 vmovq %rcx,%xmm4 + +[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx-scalar-2.s b/gas/testsuite/gas/i386/x86-64-avx-scalar-2.s new file mode 100644 index 00000000000..679ce517baf --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-scalar-2.s @@ -0,0 +1,31 @@ +# Check VEX.128 scalar instructions with -mavxscalar=256 -msse2avx + + .allow_index_reg + .text +_start: + movd %xmm4,(%rcx) + movd %xmm4,%ecx + movd (%rcx),%xmm4 + movd %ecx,%xmm4 + + movd %rcx,%xmm4 + movd %xmm4,%rcx + + movq %xmm4,(%rcx) + movq %xmm4,%rcx + movq (%rcx),%xmm4 + movq %rcx,%xmm4 + + vmovd %xmm4,(%rcx) + vmovd %xmm4,%ecx + vmovd (%rcx),%xmm4 + vmovd %ecx,%xmm4 + + vmovd %xmm4,%rcx + vmovd %rcx,%xmm4 + + vmovq %xmm4,(%rcx) + vmovq %xmm4,%rcx + vmovq (%rcx),%xmm4 + vmovq %rcx,%xmm4 + vmovq %xmm4,%xmm6 diff --git a/gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d b/gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d index 6362bf170fa..c87dd52dc04 100644 --- a/gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d +++ b/gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d @@ -15,12 +15,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 fd 2e 21 vucomisd xmm4,QWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 ff 10 21 vmovsd xmm4,QWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 ff 11 21 vmovsd QWORD PTR \[rcx\],xmm4 -[ ]*[a-f0-9]+: c4 e1 fd 7e e1 vmovq rcx,xmm4 -[ ]*[a-f0-9]+: c4 e1 fd 6e e1 vmovq xmm4,rcx -[ ]*[a-f0-9]+: c4 e1 fd 7e e1 vmovq rcx,xmm4 -[ ]*[a-f0-9]+: c4 e1 fd 6e e1 vmovq xmm4,rcx -[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq QWORD PTR \[rcx\],xmm4 -[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq xmm4,QWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 ff 2d cc vcvtsd2si ecx,xmm4 [ ]*[a-f0-9]+: c5 ff 2d 09 vcvtsd2si ecx,QWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 ff 2c cc vcvttsd2si ecx,xmm4 @@ -207,10 +201,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 fc 2e 21 vucomiss xmm4,DWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 fe 10 21 vmovss xmm4,DWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 fe 11 21 vmovss DWORD PTR \[rcx\],xmm4 -[ ]*[a-f0-9]+: c5 fd 7e e1 vmovd ecx,xmm4 -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd DWORD PTR \[rcx\],xmm4 -[ ]*[a-f0-9]+: c5 fd 6e e1 vmovd xmm4,ecx -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd xmm4,DWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 fe 2d cc vcvtss2si ecx,xmm4 [ ]*[a-f0-9]+: c5 fe 2d 09 vcvtss2si ecx,DWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 fe 2c cc vcvttss2si ecx,xmm4 @@ -227,42 +217,24 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ce c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[rcx\] [ ]*[a-f0-9]+: c4 e3 4d 0a d4 07 vroundss xmm2,xmm6,xmm4,0x7 [ ]*[a-f0-9]+: c4 e3 4d 0a 11 07 vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x7 -[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4 [ ]*[a-f0-9]+: c5 cf 10 d4 vmovsd xmm2,xmm6,xmm4 [ ]*[a-f0-9]+: c5 ce 10 d4 vmovss xmm2,xmm6,xmm4 -[ ]*[a-f0-9]+: c5 7d 7e 04 25 78 56 34 12 vmovd DWORD PTR ds:0x12345678,xmm8 [ ]*[a-f0-9]+: c5 3f 2a 3c 25 78 56 34 12 vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0x12345678 -[ ]*[a-f0-9]+: c5 7d 7e 45 00 vmovd DWORD PTR \[rbp\+0x0\],xmm8 [ ]*[a-f0-9]+: c5 3f 2a 7d 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+0x0\] -[ ]*[a-f0-9]+: c5 7d 7e 04 24 vmovd DWORD PTR \[rsp\],xmm8 [ ]*[a-f0-9]+: c5 3f 2a 3c 24 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\] -[ ]*[a-f0-9]+: c5 7d 7e 85 99 00 00 00 vmovd DWORD PTR \[rbp\+0x99\],xmm8 [ ]*[a-f0-9]+: c5 3f 2a bd 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+0x99\] -[ ]*[a-f0-9]+: c4 41 7d 7e 87 99 00 00 00 vmovd DWORD PTR \[r15\+0x99\],xmm8 [ ]*[a-f0-9]+: c4 41 3f 2a bf 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[r15\+0x99\] -[ ]*[a-f0-9]+: c5 7d 7e 05 99 00 00 00 vmovd DWORD PTR \[rip\+0x99\],xmm8 # 4f9 <_start\+0x4f9> -[ ]*[a-f0-9]+: c5 3f 2a 3d 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rip\+0x99\] # 501 <_start\+0x501> -[ ]*[a-f0-9]+: c5 7d 7e 84 24 99 00 00 00 vmovd DWORD PTR \[rsp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c5 3f 2a 3d 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rip\+0x99\] # [a-f0-9]+ <_start\+0x[a-f0-9]+> [ ]*[a-f0-9]+: c5 3f 2a bc 24 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\+0x99\] -[ ]*[a-f0-9]+: c4 41 7d 7e 84 24 99 00 00 00 vmovd DWORD PTR \[r12\+0x99\],xmm8 [ ]*[a-f0-9]+: c4 41 3f 2a bc 24 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[r12\+0x99\] -[ ]*[a-f0-9]+: c5 7d 7e 04 25 67 ff ff ff vmovd DWORD PTR ds:0xffffffffffffff67,xmm8 [ ]*[a-f0-9]+: c5 3f 2a 3c 25 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0xffffffffffffff67 -[ ]*[a-f0-9]+: c5 7d 7e 04 65 67 ff ff ff vmovd DWORD PTR \[riz\*2-0x99\],xmm8 [ ]*[a-f0-9]+: c5 3f 2a 3c 65 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[riz\*2-0x99\] -[ ]*[a-f0-9]+: c5 7d 7e 84 23 67 ff ff ff vmovd DWORD PTR \[rbx\+riz\*1-0x99\],xmm8 [ ]*[a-f0-9]+: c5 3f 2a bc 23 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbx\+riz\*1-0x99\] -[ ]*[a-f0-9]+: c5 7d 7e 84 63 67 ff ff ff vmovd DWORD PTR \[rbx\+riz\*2-0x99\],xmm8 [ ]*[a-f0-9]+: c5 3f 2a bc 63 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbx\+riz\*2-0x99\] -[ ]*[a-f0-9]+: c4 01 7d 7e 84 bc 67 ff ff ff vmovd DWORD PTR \[r12\+r15\*4-0x99\],xmm8 [ ]*[a-f0-9]+: c4 01 3f 2a bc bc 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[r12\+r15\*4-0x99\] -[ ]*[a-f0-9]+: c4 01 7d 7e 84 f8 67 ff ff ff vmovd DWORD PTR \[r8\+r15\*8-0x99\],xmm8 [ ]*[a-f0-9]+: c4 01 3f 2a bc f8 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[r8\+r15\*8-0x99\] -[ ]*[a-f0-9]+: c4 21 7d 7e 84 ad 67 ff ff ff vmovd DWORD PTR \[rbp\+r13\*4-0x99\],xmm8 [ ]*[a-f0-9]+: c4 21 3f 2a bc ad 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+r13\*4-0x99\] -[ ]*[a-f0-9]+: c4 21 7d 7e 84 24 67 ff ff ff vmovd DWORD PTR \[rsp\+r12\*1-0x99\],xmm8 [ ]*[a-f0-9]+: c4 21 3f 2a bc 24 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\+r12\*1-0x99\] -[ ]*[a-f0-9]+: c4 41 7d 7e c0 vmovd r8d,xmm8 [ ]*[a-f0-9]+: c4 41 7f 2d c0 vcvtsd2si r8d,xmm8 [ ]*[a-f0-9]+: c4 41 3f 2a f8 vcvtsi2sd xmm15,xmm8,r8d [ ]*[a-f0-9]+: c4 61 ff 2d 01 vcvtsd2si r8,QWORD PTR \[rcx\] @@ -277,16 +249,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ff 10 21 vmovsd xmm4,QWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 ff 11 21 vmovsd QWORD PTR \[rcx\],xmm4 [ ]*[a-f0-9]+: c5 ff 11 21 vmovsd QWORD PTR \[rcx\],xmm4 -[ ]*[a-f0-9]+: c4 e1 fd 7e e1 vmovq rcx,xmm4 -[ ]*[a-f0-9]+: c4 e1 fd 6e e1 vmovq xmm4,rcx -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd DWORD PTR \[rcx\],xmm4 -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd xmm4,DWORD PTR \[rcx\] -[ ]*[a-f0-9]+: c4 e1 fd 7e e1 vmovq rcx,xmm4 -[ ]*[a-f0-9]+: c4 e1 fd 6e e1 vmovq xmm4,rcx -[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq QWORD PTR \[rcx\],xmm4 -[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq xmm4,QWORD PTR \[rcx\] -[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq QWORD PTR \[rcx\],xmm4 -[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq xmm4,QWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 ff 2d cc vcvtsd2si ecx,xmm4 [ ]*[a-f0-9]+: c5 ff 2d 09 vcvtsd2si ecx,QWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 ff 2d 09 vcvtsd2si ecx,QWORD PTR \[rcx\] @@ -567,12 +529,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 fe 10 21 vmovss xmm4,DWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 fe 11 21 vmovss DWORD PTR \[rcx\],xmm4 [ ]*[a-f0-9]+: c5 fe 11 21 vmovss DWORD PTR \[rcx\],xmm4 -[ ]*[a-f0-9]+: c5 fd 7e e1 vmovd ecx,xmm4 -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd DWORD PTR \[rcx\],xmm4 -[ ]*[a-f0-9]+: c5 fd 6e e1 vmovd xmm4,ecx -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd xmm4,DWORD PTR \[rcx\] -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd DWORD PTR \[rcx\],xmm4 -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd xmm4,DWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 fe 2d cc vcvtss2si ecx,xmm4 [ ]*[a-f0-9]+: c5 fe 2d 09 vcvtss2si ecx,DWORD PTR \[rcx\] [ ]*[a-f0-9]+: c5 fe 2d 09 vcvtss2si ecx,DWORD PTR \[rcx\] @@ -595,40 +551,23 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c4 e3 4d 0a d4 07 vroundss xmm2,xmm6,xmm4,0x7 [ ]*[a-f0-9]+: c4 e3 4d 0a 11 07 vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x7 [ ]*[a-f0-9]+: c4 e3 4d 0a 11 07 vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x7 -[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4 [ ]*[a-f0-9]+: c5 cf 10 d4 vmovsd xmm2,xmm6,xmm4 [ ]*[a-f0-9]+: c5 ce 10 d4 vmovss xmm2,xmm6,xmm4 -[ ]*[a-f0-9]+: c5 7d 7e 04 25 78 56 34 12 vmovd DWORD PTR ds:0x12345678,xmm8 [ ]*[a-f0-9]+: c5 3f 2a 3c 25 78 56 34 12 vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0x12345678 -[ ]*[a-f0-9]+: c5 7d 7e 45 00 vmovd DWORD PTR \[rbp\+0x0\],xmm8 [ ]*[a-f0-9]+: c5 3f 2a 7d 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+0x0\] -[ ]*[a-f0-9]+: c5 7d 7e 85 99 00 00 00 vmovd DWORD PTR \[rbp\+0x99\],xmm8 [ ]*[a-f0-9]+: c5 3f 2a bd 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+0x99\] -[ ]*[a-f0-9]+: c4 41 7d 7e 87 99 00 00 00 vmovd DWORD PTR \[r15\+0x99\],xmm8 [ ]*[a-f0-9]+: c4 41 3f 2a bf 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[r15\+0x99\] -[ ]*[a-f0-9]+: c5 7d 7e 05 99 00 00 00 vmovd DWORD PTR \[rip\+0x99\],xmm8 # c32 <_start\+0xc32> -[ ]*[a-f0-9]+: c5 3f 2a 3d 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rip\+0x99\] # c3a <_start\+0xc3a> -[ ]*[a-f0-9]+: c5 7d 7e 84 24 99 00 00 00 vmovd DWORD PTR \[rsp\+0x99\],xmm8 +[ ]*[a-f0-9]+: c5 3f 2a 3d 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rip\+0x99\] # [a-f0-9]+ <_start\+0x[a-f0-9]+> [ ]*[a-f0-9]+: c5 3f 2a bc 24 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\+0x99\] -[ ]*[a-f0-9]+: c4 41 7d 7e 84 24 99 00 00 00 vmovd DWORD PTR \[r12\+0x99\],xmm8 [ ]*[a-f0-9]+: c4 41 3f 2a bc 24 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[r12\+0x99\] -[ ]*[a-f0-9]+: c5 7d 7e 04 25 67 ff ff ff vmovd DWORD PTR ds:0xffffffffffffff67,xmm8 [ ]*[a-f0-9]+: c5 3f 2a 3c 25 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0xffffffffffffff67 -[ ]*[a-f0-9]+: c5 7d 7e 04 65 67 ff ff ff vmovd DWORD PTR \[riz\*2-0x99\],xmm8 [ ]*[a-f0-9]+: c5 3f 2a 3c 65 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[riz\*2-0x99\] -[ ]*[a-f0-9]+: c5 7d 7e 84 23 67 ff ff ff vmovd DWORD PTR \[rbx\+riz\*1-0x99\],xmm8 [ ]*[a-f0-9]+: c5 3f 2a bc 23 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbx\+riz\*1-0x99\] -[ ]*[a-f0-9]+: c5 7d 7e 84 63 67 ff ff ff vmovd DWORD PTR \[rbx\+riz\*2-0x99\],xmm8 [ ]*[a-f0-9]+: c5 3f 2a bc 63 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbx\+riz\*2-0x99\] -[ ]*[a-f0-9]+: c4 01 7d 7e 84 bc 67 ff ff ff vmovd DWORD PTR \[r12\+r15\*4-0x99\],xmm8 [ ]*[a-f0-9]+: c4 01 3f 2a bc bc 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[r12\+r15\*4-0x99\] -[ ]*[a-f0-9]+: c4 01 7d 7e 84 f8 67 ff ff ff vmovd DWORD PTR \[r8\+r15\*8-0x99\],xmm8 [ ]*[a-f0-9]+: c4 01 3f 2a bc f8 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[r8\+r15\*8-0x99\] -[ ]*[a-f0-9]+: c4 21 7d 7e 84 a5 67 ff ff ff vmovd DWORD PTR \[rbp\+r12\*4-0x99\],xmm8 [ ]*[a-f0-9]+: c4 21 3f 2a bc a5 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+r12\*4-0x99\] -[ ]*[a-f0-9]+: c4 21 7d 7e 84 2c 67 ff ff ff vmovd DWORD PTR \[rsp\+r13\*1-0x99\],xmm8 [ ]*[a-f0-9]+: c4 21 3f 2a bc 2c 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\+r13\*1-0x99\] -[ ]*[a-f0-9]+: c4 41 7d 7e c0 vmovd r8d,xmm8 [ ]*[a-f0-9]+: c4 41 7f 2d c0 vcvtsd2si r8d,xmm8 [ ]*[a-f0-9]+: c4 41 3f 2a f8 vcvtsi2sd xmm15,xmm8,r8d [ ]*[a-f0-9]+: c4 61 ff 2d 01 vcvtsd2si r8,QWORD PTR \[rcx\] diff --git a/gas/testsuite/gas/i386/x86-64-avx-scalar.d b/gas/testsuite/gas/i386/x86-64-avx-scalar.d index 93f14fd9bdd..5b2244d796f 100644 --- a/gas/testsuite/gas/i386/x86-64-avx-scalar.d +++ b/gas/testsuite/gas/i386/x86-64-avx-scalar.d @@ -14,12 +14,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 fd 2e 21 vucomisd \(%rcx\),%xmm4 [ ]*[a-f0-9]+: c5 ff 10 21 vmovsd \(%rcx\),%xmm4 [ ]*[a-f0-9]+: c5 ff 11 21 vmovsd %xmm4,\(%rcx\) -[ ]*[a-f0-9]+: c4 e1 fd 7e e1 vmovq %xmm4,%rcx -[ ]*[a-f0-9]+: c4 e1 fd 6e e1 vmovq %rcx,%xmm4 -[ ]*[a-f0-9]+: c4 e1 fd 7e e1 vmovq %xmm4,%rcx -[ ]*[a-f0-9]+: c4 e1 fd 6e e1 vmovq %rcx,%xmm4 -[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%rcx\) -[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%rcx\),%xmm4 [ ]*[a-f0-9]+: c5 ff 2d cc vcvtsd2si %xmm4,%ecx [ ]*[a-f0-9]+: c5 ff 2d 09 vcvtsd2si \(%rcx\),%ecx [ ]*[a-f0-9]+: c5 ff 2c cc vcvttsd2si %xmm4,%ecx @@ -206,10 +200,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 fc 2e 21 vucomiss \(%rcx\),%xmm4 [ ]*[a-f0-9]+: c5 fe 10 21 vmovss \(%rcx\),%xmm4 [ ]*[a-f0-9]+: c5 fe 11 21 vmovss %xmm4,\(%rcx\) -[ ]*[a-f0-9]+: c5 fd 7e e1 vmovd %xmm4,%ecx -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd %xmm4,\(%rcx\) -[ ]*[a-f0-9]+: c5 fd 6e e1 vmovd %ecx,%xmm4 -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd \(%rcx\),%xmm4 [ ]*[a-f0-9]+: c5 fe 2d cc vcvtss2si %xmm4,%ecx [ ]*[a-f0-9]+: c5 fe 2d 09 vcvtss2si \(%rcx\),%ecx [ ]*[a-f0-9]+: c5 fe 2c cc vcvttss2si %xmm4,%ecx @@ -226,42 +216,24 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ce c2 11 07 vcmpordss \(%rcx\),%xmm6,%xmm2 [ ]*[a-f0-9]+: c4 e3 4d 0a d4 07 vroundss \$0x7,%xmm4,%xmm6,%xmm2 [ ]*[a-f0-9]+: c4 e3 4d 0a 11 07 vroundss \$0x7,\(%rcx\),%xmm6,%xmm2 -[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6 [ ]*[a-f0-9]+: c5 cf 10 d4 vmovsd %xmm4,%xmm6,%xmm2 [ ]*[a-f0-9]+: c5 ce 10 d4 vmovss %xmm4,%xmm6,%xmm2 -[ ]*[a-f0-9]+: c5 7d 7e 04 25 78 56 34 12 vmovd %xmm8,0x12345678 [ ]*[a-f0-9]+: c5 3f 2a 3c 25 78 56 34 12 vcvtsi2sdl 0x12345678,%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 45 00 vmovd %xmm8,0x0\(%rbp\) [ ]*[a-f0-9]+: c5 3f 2a 7d 00 vcvtsi2sdl 0x0\(%rbp\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 04 24 vmovd %xmm8,\(%rsp\) [ ]*[a-f0-9]+: c5 3f 2a 3c 24 vcvtsi2sdl \(%rsp\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 85 99 00 00 00 vmovd %xmm8,0x99\(%rbp\) [ ]*[a-f0-9]+: c5 3f 2a bd 99 00 00 00 vcvtsi2sdl 0x99\(%rbp\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 41 7d 7e 87 99 00 00 00 vmovd %xmm8,0x99\(%r15\) [ ]*[a-f0-9]+: c4 41 3f 2a bf 99 00 00 00 vcvtsi2sdl 0x99\(%r15\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 05 99 00 00 00 vmovd %xmm8,0x99\(%rip\) # 4f9 <_start\+0x4f9> -[ ]*[a-f0-9]+: c5 3f 2a 3d 99 00 00 00 vcvtsi2sdl 0x99\(%rip\),%xmm8,%xmm15 # 501 <_start\+0x501> -[ ]*[a-f0-9]+: c5 7d 7e 84 24 99 00 00 00 vmovd %xmm8,0x99\(%rsp\) +[ ]*[a-f0-9]+: c5 3f 2a 3d 99 00 00 00 vcvtsi2sdl 0x99\(%rip\),%xmm8,%xmm15 # [a-f0-9]+ <_start\+0x[a-f0-9]+> [ ]*[a-f0-9]+: c5 3f 2a bc 24 99 00 00 00 vcvtsi2sdl 0x99\(%rsp\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 41 7d 7e 84 24 99 00 00 00 vmovd %xmm8,0x99\(%r12\) [ ]*[a-f0-9]+: c4 41 3f 2a bc 24 99 00 00 00 vcvtsi2sdl 0x99\(%r12\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 04 25 67 ff ff ff vmovd %xmm8,0xffffffffffffff67 [ ]*[a-f0-9]+: c5 3f 2a 3c 25 67 ff ff ff vcvtsi2sdl 0xffffffffffffff67,%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 04 65 67 ff ff ff vmovd %xmm8,-0x99\(,%riz,2\) [ ]*[a-f0-9]+: c5 3f 2a 3c 65 67 ff ff ff vcvtsi2sdl -0x99\(,%riz,2\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 84 23 67 ff ff ff vmovd %xmm8,-0x99\(%rbx,%riz,1\) [ ]*[a-f0-9]+: c5 3f 2a bc 23 67 ff ff ff vcvtsi2sdl -0x99\(%rbx,%riz,1\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 84 63 67 ff ff ff vmovd %xmm8,-0x99\(%rbx,%riz,2\) [ ]*[a-f0-9]+: c5 3f 2a bc 63 67 ff ff ff vcvtsi2sdl -0x99\(%rbx,%riz,2\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 01 7d 7e 84 bc 67 ff ff ff vmovd %xmm8,-0x99\(%r12,%r15,4\) [ ]*[a-f0-9]+: c4 01 3f 2a bc bc 67 ff ff ff vcvtsi2sdl -0x99\(%r12,%r15,4\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 01 7d 7e 84 f8 67 ff ff ff vmovd %xmm8,-0x99\(%r8,%r15,8\) [ ]*[a-f0-9]+: c4 01 3f 2a bc f8 67 ff ff ff vcvtsi2sdl -0x99\(%r8,%r15,8\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 21 7d 7e 84 ad 67 ff ff ff vmovd %xmm8,-0x99\(%rbp,%r13,4\) [ ]*[a-f0-9]+: c4 21 3f 2a bc ad 67 ff ff ff vcvtsi2sdl -0x99\(%rbp,%r13,4\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 21 7d 7e 84 24 67 ff ff ff vmovd %xmm8,-0x99\(%rsp,%r12,1\) [ ]*[a-f0-9]+: c4 21 3f 2a bc 24 67 ff ff ff vcvtsi2sdl -0x99\(%rsp,%r12,1\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 41 7d 7e c0 vmovd %xmm8,%r8d [ ]*[a-f0-9]+: c4 41 7f 2d c0 vcvtsd2si %xmm8,%r8d [ ]*[a-f0-9]+: c4 41 3f 2a f8 vcvtsi2sd %r8d,%xmm8,%xmm15 [ ]*[a-f0-9]+: c4 61 ff 2d 01 vcvtsd2si \(%rcx\),%r8 @@ -276,16 +248,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 ff 10 21 vmovsd \(%rcx\),%xmm4 [ ]*[a-f0-9]+: c5 ff 11 21 vmovsd %xmm4,\(%rcx\) [ ]*[a-f0-9]+: c5 ff 11 21 vmovsd %xmm4,\(%rcx\) -[ ]*[a-f0-9]+: c4 e1 fd 7e e1 vmovq %xmm4,%rcx -[ ]*[a-f0-9]+: c4 e1 fd 6e e1 vmovq %rcx,%xmm4 -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd %xmm4,\(%rcx\) -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd \(%rcx\),%xmm4 -[ ]*[a-f0-9]+: c4 e1 fd 7e e1 vmovq %xmm4,%rcx -[ ]*[a-f0-9]+: c4 e1 fd 6e e1 vmovq %rcx,%xmm4 -[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%rcx\) -[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%rcx\),%xmm4 -[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%rcx\) -[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%rcx\),%xmm4 [ ]*[a-f0-9]+: c5 ff 2d cc vcvtsd2si %xmm4,%ecx [ ]*[a-f0-9]+: c5 ff 2d 09 vcvtsd2si \(%rcx\),%ecx [ ]*[a-f0-9]+: c5 ff 2d 09 vcvtsd2si \(%rcx\),%ecx @@ -566,12 +528,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c5 fe 10 21 vmovss \(%rcx\),%xmm4 [ ]*[a-f0-9]+: c5 fe 11 21 vmovss %xmm4,\(%rcx\) [ ]*[a-f0-9]+: c5 fe 11 21 vmovss %xmm4,\(%rcx\) -[ ]*[a-f0-9]+: c5 fd 7e e1 vmovd %xmm4,%ecx -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd %xmm4,\(%rcx\) -[ ]*[a-f0-9]+: c5 fd 6e e1 vmovd %ecx,%xmm4 -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd \(%rcx\),%xmm4 -[ ]*[a-f0-9]+: c5 fd 7e 21 vmovd %xmm4,\(%rcx\) -[ ]*[a-f0-9]+: c5 fd 6e 21 vmovd \(%rcx\),%xmm4 [ ]*[a-f0-9]+: c5 fe 2d cc vcvtss2si %xmm4,%ecx [ ]*[a-f0-9]+: c5 fe 2d 09 vcvtss2si \(%rcx\),%ecx [ ]*[a-f0-9]+: c5 fe 2d 09 vcvtss2si \(%rcx\),%ecx @@ -594,40 +550,23 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c4 e3 4d 0a d4 07 vroundss \$0x7,%xmm4,%xmm6,%xmm2 [ ]*[a-f0-9]+: c4 e3 4d 0a 11 07 vroundss \$0x7,\(%rcx\),%xmm6,%xmm2 [ ]*[a-f0-9]+: c4 e3 4d 0a 11 07 vroundss \$0x7,\(%rcx\),%xmm6,%xmm2 -[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6 [ ]*[a-f0-9]+: c5 cf 10 d4 vmovsd %xmm4,%xmm6,%xmm2 [ ]*[a-f0-9]+: c5 ce 10 d4 vmovss %xmm4,%xmm6,%xmm2 -[ ]*[a-f0-9]+: c5 7d 7e 04 25 78 56 34 12 vmovd %xmm8,0x12345678 [ ]*[a-f0-9]+: c5 3f 2a 3c 25 78 56 34 12 vcvtsi2sdl 0x12345678,%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 45 00 vmovd %xmm8,0x0\(%rbp\) [ ]*[a-f0-9]+: c5 3f 2a 7d 00 vcvtsi2sdl 0x0\(%rbp\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 85 99 00 00 00 vmovd %xmm8,0x99\(%rbp\) [ ]*[a-f0-9]+: c5 3f 2a bd 99 00 00 00 vcvtsi2sdl 0x99\(%rbp\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 41 7d 7e 87 99 00 00 00 vmovd %xmm8,0x99\(%r15\) [ ]*[a-f0-9]+: c4 41 3f 2a bf 99 00 00 00 vcvtsi2sdl 0x99\(%r15\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 05 99 00 00 00 vmovd %xmm8,0x99\(%rip\) # c32 <_start\+0xc32> -[ ]*[a-f0-9]+: c5 3f 2a 3d 99 00 00 00 vcvtsi2sdl 0x99\(%rip\),%xmm8,%xmm15 # c3a <_start\+0xc3a> -[ ]*[a-f0-9]+: c5 7d 7e 84 24 99 00 00 00 vmovd %xmm8,0x99\(%rsp\) +[ ]*[a-f0-9]+: c5 3f 2a 3d 99 00 00 00 vcvtsi2sdl 0x99\(%rip\),%xmm8,%xmm15 # [a-f0-9]+ <_start\+0x[a-f0-9]+> [ ]*[a-f0-9]+: c5 3f 2a bc 24 99 00 00 00 vcvtsi2sdl 0x99\(%rsp\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 41 7d 7e 84 24 99 00 00 00 vmovd %xmm8,0x99\(%r12\) [ ]*[a-f0-9]+: c4 41 3f 2a bc 24 99 00 00 00 vcvtsi2sdl 0x99\(%r12\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 04 25 67 ff ff ff vmovd %xmm8,0xffffffffffffff67 [ ]*[a-f0-9]+: c5 3f 2a 3c 25 67 ff ff ff vcvtsi2sdl 0xffffffffffffff67,%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 04 65 67 ff ff ff vmovd %xmm8,-0x99\(,%riz,2\) [ ]*[a-f0-9]+: c5 3f 2a 3c 65 67 ff ff ff vcvtsi2sdl -0x99\(,%riz,2\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 84 23 67 ff ff ff vmovd %xmm8,-0x99\(%rbx,%riz,1\) [ ]*[a-f0-9]+: c5 3f 2a bc 23 67 ff ff ff vcvtsi2sdl -0x99\(%rbx,%riz,1\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c5 7d 7e 84 63 67 ff ff ff vmovd %xmm8,-0x99\(%rbx,%riz,2\) [ ]*[a-f0-9]+: c5 3f 2a bc 63 67 ff ff ff vcvtsi2sdl -0x99\(%rbx,%riz,2\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 01 7d 7e 84 bc 67 ff ff ff vmovd %xmm8,-0x99\(%r12,%r15,4\) [ ]*[a-f0-9]+: c4 01 3f 2a bc bc 67 ff ff ff vcvtsi2sdl -0x99\(%r12,%r15,4\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 01 7d 7e 84 f8 67 ff ff ff vmovd %xmm8,-0x99\(%r8,%r15,8\) [ ]*[a-f0-9]+: c4 01 3f 2a bc f8 67 ff ff ff vcvtsi2sdl -0x99\(%r8,%r15,8\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 21 7d 7e 84 a5 67 ff ff ff vmovd %xmm8,-0x99\(%rbp,%r12,4\) [ ]*[a-f0-9]+: c4 21 3f 2a bc a5 67 ff ff ff vcvtsi2sdl -0x99\(%rbp,%r12,4\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 21 7d 7e 84 2c 67 ff ff ff vmovd %xmm8,-0x99\(%rsp,%r13,1\) [ ]*[a-f0-9]+: c4 21 3f 2a bc 2c 67 ff ff ff vcvtsi2sdl -0x99\(%rsp,%r13,1\),%xmm8,%xmm15 -[ ]*[a-f0-9]+: c4 41 7d 7e c0 vmovd %xmm8,%r8d [ ]*[a-f0-9]+: c4 41 7f 2d c0 vcvtsd2si %xmm8,%r8d [ ]*[a-f0-9]+: c4 41 3f 2a f8 vcvtsi2sd %r8d,%xmm8,%xmm15 [ ]*[a-f0-9]+: c4 61 ff 2d 01 vcvtsd2si \(%rcx\),%r8 diff --git a/gas/testsuite/gas/i386/x86-64-avx-scalar.s b/gas/testsuite/gas/i386/x86-64-avx-scalar.s index 553d209878c..0f8800fc6da 100644 --- a/gas/testsuite/gas/i386/x86-64-avx-scalar.s +++ b/gas/testsuite/gas/i386/x86-64-avx-scalar.s @@ -16,15 +16,6 @@ _start: # Tests for op xmm, mem64 vmovsd %xmm4,(%rcx) -# Tests for op xmm, regq/mem64 -# Tests for op regq/mem64, xmm - vmovd %xmm4,%rcx - vmovd %rcx,%xmm4 - vmovq %xmm4,%rcx - vmovq %rcx,%xmm4 - vmovq %xmm4,(%rcx) - vmovq (%rcx),%xmm4 - # Tests for op xmm/mem64, regl vcvtsd2si %xmm4,%ecx vcvtsd2si (%rcx),%ecx @@ -229,13 +220,6 @@ _start: # Tests for op xmm, mem32 vmovss %xmm4,(%rcx) -# Tests for op xmm, regl/mem32 -# Tests for op regl/mem32, xmm - vmovd %xmm4,%ecx - vmovd %xmm4,(%rcx) - vmovd %ecx,%xmm4 - vmovd (%rcx),%xmm4 - # Tests for op xmm/mem32, regl vcvtss2si %xmm4,%ecx vcvtss2si (%rcx),%ecx @@ -260,48 +244,28 @@ _start: vroundss $7,%xmm4,%xmm6,%xmm2 vroundss $7,(%rcx),%xmm6,%xmm2 -# Tests for op xmm, xmm - vmovq %xmm4,%xmm6 - # Tests for op xmm, xmm, xmm vmovsd %xmm4,%xmm6,%xmm2 vmovss %xmm4,%xmm6,%xmm2 #Tests with different memory and register operands. - vmovd %xmm8,0x12345678 vcvtsi2sdl 0x12345678,%xmm8,%xmm15 - vmovd %xmm8,(%rbp) vcvtsi2sdl (%rbp),%xmm8,%xmm15 - vmovd %xmm8,(%rsp) vcvtsi2sdl (%rsp),%xmm8,%xmm15 - vmovd %xmm8,0x99(%rbp) vcvtsi2sdl 0x99(%rbp),%xmm8,%xmm15 - vmovd %xmm8,0x99(%r15) vcvtsi2sdl 0x99(%r15),%xmm8,%xmm15 - vmovd %xmm8,0x99(%rip) vcvtsi2sdl 0x99(%rip),%xmm8,%xmm15 - vmovd %xmm8,0x99(%rsp) vcvtsi2sdl 0x99(%rsp),%xmm8,%xmm15 - vmovd %xmm8,0x99(%r12) vcvtsi2sdl 0x99(%r12),%xmm8,%xmm15 - vmovd %xmm8,-0x99(,%riz) vcvtsi2sdl -0x99(,%riz),%xmm8,%xmm15 - vmovd %xmm8,-0x99(,%riz,2) vcvtsi2sdl -0x99(,%riz,2),%xmm8,%xmm15 - vmovd %xmm8,-0x99(%rbx,%riz) vcvtsi2sdl -0x99(%rbx,%riz),%xmm8,%xmm15 - vmovd %xmm8,-0x99(%rbx,%riz,2) vcvtsi2sdl -0x99(%rbx,%riz,2),%xmm8,%xmm15 - vmovd %xmm8,-0x99(%r12,%r15,4) vcvtsi2sdl -0x99(%r12,%r15,4),%xmm8,%xmm15 - vmovd %xmm8,-0x99(%r8,%r15,8) vcvtsi2sdl -0x99(%r8,%r15,8),%xmm8,%xmm15 - vmovd %xmm8,-0x99(%rbp,%r13,4) vcvtsi2sdl -0x99(%rbp,%r13,4),%xmm8,%xmm15 - vmovd %xmm8,-0x99(%rsp,%r12,1) vcvtsi2sdl -0x99(%rsp,%r12,1),%xmm8,%xmm15 # Tests for all register operands. - vmovd %xmm8,%r8d vcvtsd2si %xmm8,%r8d vcvtsi2sdl %r8d,%xmm8,%xmm15 # Tests for different memory/register operand @@ -326,19 +290,6 @@ _start: vmovsd QWORD PTR [rcx],xmm4 vmovsd [rcx],xmm4 -# Tests for op xmm, regq/mem64 -# Tests for op regq/mem64, xmm - vmovd rcx,xmm4 - vmovd xmm4,rcx - vmovd [rcx],xmm4 - vmovd xmm4,[rcx] - vmovq rcx,xmm4 - vmovq xmm4,rcx - vmovq QWORD PTR [rcx],xmm4 - vmovq xmm4,QWORD PTR [rcx] - vmovq [rcx],xmm4 - vmovq xmm4,[rcx] - # Tests for op xmm/mem64, regl vcvtsd2si ecx,xmm4 vcvtsd2si ecx,QWORD PTR [rcx] @@ -637,15 +588,6 @@ _start: vmovss DWORD PTR [rcx],xmm4 vmovss [rcx],xmm4 -# Tests for op xmm, regl/mem32 -# Tests for op regl/mem32, xmm - vmovd ecx,xmm4 - vmovd DWORD PTR [rcx],xmm4 - vmovd xmm4,ecx - vmovd xmm4,DWORD PTR [rcx] - vmovd [rcx],xmm4 - vmovd xmm4,[rcx] - # Tests for op xmm/mem32, regl vcvtss2si ecx,xmm4 vcvtss2si ecx,DWORD PTR [rcx] @@ -676,46 +618,27 @@ _start: vroundss xmm2,xmm6,DWORD PTR [rcx],7 vroundss xmm2,xmm6,[rcx],7 -# Tests for op xmm, xmm - vmovq xmm6,xmm4 - # Tests for op xmm, xmm, xmm vmovsd xmm2,xmm6,xmm4 vmovss xmm2,xmm6,xmm4 #Tests with different memory and register operands. - vmovd DWORD PTR ds:0x12345678,xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0x12345678 - vmovd DWORD PTR [rbp],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [rbp] - vmovd DWORD PTR [rbp+0x99],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [rbp+0x99] - vmovd DWORD PTR [r15+0x99],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [r15+0x99] - vmovd DWORD PTR [rip+0x99],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [rip+0x99] - vmovd DWORD PTR [rsp+0x99],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [rsp+0x99] - vmovd DWORD PTR [r12+0x99],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [r12+0x99] - vmovd DWORD PTR [riz*1-0x99],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [riz*1-0x99] - vmovd DWORD PTR [riz*2-0x99],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [riz*2-0x99] - vmovd DWORD PTR [rbx+riz*1-0x99],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [rbx+riz*1-0x99] - vmovd DWORD PTR [rbx+riz*2-0x99],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [rbx+riz*2-0x99] - vmovd DWORD PTR [r12+r15*4-0x99],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [r12+r15*4-0x99] - vmovd DWORD PTR [r8+r15*8-0x99],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [r8+r15*8-0x99] - vmovd DWORD PTR [rbp+r12*4-0x99],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [rbp+r12*4-0x99] - vmovd DWORD PTR [rsp+r13*1-0x99],xmm8 vcvtsi2sd xmm15,xmm8,DWORD PTR [rsp+r13*1-0x99] # Tests for all register operands. - vmovd r8d,xmm8 vcvtsd2si r8d,xmm8 vcvtsi2sd xmm15,xmm8,r8d # Tests for different memory/register operand diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 76c554fd9a3..4960430ee7b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2018-09-17 H.J. Lu + + PR gas/23665 + * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and + VEX_LEN_0F7E_P_2 entries. + * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq. + * i386-tbl.h: Regenerated. + 2018-09-17 H.J. Lu * i386-dis.c (VZERO_Fixup): Removed. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 02bf3404bac..89b824c85ca 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -9433,7 +9433,6 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F6E_P_2 */ { { "vmovK", { XMScalar, Edq }, 0 }, - { "vmovK", { XMScalar, Edq }, 0 }, }, /* VEX_LEN_0F77_P_1 */ @@ -9450,7 +9449,6 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F7E_P_2 */ { { "vmovK", { Edq, XMScalar }, 0 }, - { "vmovK", { Edq, XMScalar }, 0 }, }, /* VEX_LEN_0F90_P_0 */ diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 512d89d9b01..70f78873a10 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -943,8 +943,8 @@ emms, 0, 0xf77, None, 2, CpuMMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu // copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's // spec). AMD's spec, having been in existence for much longer, failed to // recognize that and specified movd for 32- and 64-bit operations. -movd, 2, 0x666e, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, RegXMM } -movd, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|SSE2AVX, { Reg64|BaseIndex, RegXMM } +movd, 2, 0x666e, None, 1, CpuAVX, D|Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, RegXMM } +movd, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|SSE2AVX, { Reg64|BaseIndex, RegXMM } movd, 2, 0x660f6e, None, 2, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM } movd, 2, 0x660f6e, None, 2, CpuSSE2|Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|BaseIndex, RegXMM } movd, 2, 0xf6e, None, 2, CpuMMX, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegMMX } @@ -956,9 +956,9 @@ movq, 2, 0xa0, None, 1, Cpu64, D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu movq, 2, 0x88, None, 1, Cpu64, D|W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|HLEPrefixOk=3, { Reg64, Reg64|Unspecified|Qword|BaseIndex } movq, 2, 0xc6, 0x0, 1, Cpu64, W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|HLEPrefixOk=3|Optimize, { Imm32S, Reg64|Qword|Unspecified|BaseIndex } movq, 2, 0xb0, None, 1, Cpu64, W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Imm64, Reg64 } -movq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -movq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } -movq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM } +movq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=1|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +movq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=1|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } +movq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM } movq, 2, 0xf30f7e, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM } movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM } movq, 2, 0x660f6e, None, 2, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } @@ -2010,8 +2010,8 @@ vmovaps, 2, 0x28, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|N // by Intel AVX spec). To avoid extra template in gcc x86 backend and // support assembler for AMD64, we accept 64bit operand on vmovd so // that we can use one template for both SSE and AVX instructions. -vmovd, 2, 0x666e, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM } -vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|RegMem, RegXMM } +vmovd, 2, 0x666e, None, 1, CpuAVX, D|Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|RegMem, RegXMM } vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM } vmovdqa, 2, 0x666f, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } @@ -2034,7 +2034,7 @@ vmovntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize| vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=1|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=1|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } -vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } +vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } vmovsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM } vmovsd, 3, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM } vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 0b1d2a4bc29..c4145c690f2 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -10517,7 +10517,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 3, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, @@ -10534,7 +10534,7 @@ const insn_template i386_optab[] = 0, 0, 0, 1, 0, 0 } }, { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 3, 0, 2, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 2, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, @@ -10687,7 +10687,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, - 3, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, @@ -10704,7 +10704,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, - 3, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, @@ -10721,7 +10721,7 @@ const insn_template i386_optab[] = 0, 0, 0, 1, 0, 0 } }, { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 3, 0, 2, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 2, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, @@ -35963,7 +35963,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, @@ -35980,7 +35980,7 @@ const insn_template i386_optab[] = 0, 0, 0, 1, 0, 0 } }, { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 3, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, @@ -36713,7 +36713,7 @@ const insn_template i386_optab[] = 0, 0, 0, 1, 0, 0 } }, { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 3, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,