From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 17 Jun 2018 05:20:43 +0000 (+0100)
Subject: screenshot of rishabhs gpiomux redesign
X-Git-Tag: convert-csv-opcode-to-binary~5192
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d5fddd849979c05695a0c67deae7e893a2500f55;p=libreriscv.git

screenshot of rishabhs gpiomux redesign
---

diff --git a/shakti/m_class/mygpiomux.jpg b/shakti/m_class/mygpiomux.jpg
index d75949f7a..cca38e05c 100644
Binary files a/shakti/m_class/mygpiomux.jpg and b/shakti/m_class/mygpiomux.jpg differ
diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 5e8b8ff31..0fc04eb5c 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -124,15 +124,16 @@
 \frame{\frametitle{How does Simple-V relate to RVV? What's different?}
 
  \begin{itemize}
-   \item RVV very heavy-duty (excellent for supercomputing)\vspace{8pt}
-   \item Simple-V abstracts parallelism (based on best of RVV)\vspace{8pt}
-   \item Graded levels: hardware, hybrid or traps (fit impl. need)\vspace{8pt}
-   \item Even Compressed become vectorised (RVV can't)\vspace{8pt}
-   \item No polymorphism in SV (too complex)\vspace{8pt}
+   \item RVV very heavy-duty (excellent for supercomputing)\vspace{4pt}
+   \item Simple-V abstracts parallelism (based on best of RVV)\vspace{4pt}
+   \item Graded levels: hardware, hybrid or traps (fit impl. need)\vspace{4pt}
+   \item Even Compressed become vectorised (RVV can't)\vspace{4pt}
+   \item No polymorphism in SV (too complex)\vspace{4pt}
   \end{itemize}
   What Simple-V is not:\vspace{4pt}
    \begin{itemize}
-   \item A full supercomputer-level Vector Proposal
+   \item A full supercomputer-level Vector Proposal\\
+	     (it's not actually a Vector Proposal at all!)
    \item A replacement for RVV (SV is designed to be over-ridden\\
 	     by - or augmented to become - RVV)
   \end{itemize}
@@ -153,7 +154,7 @@
    \begin{itemize}
    \item All LOAD/STORE (inc. Compressed, Int/FP versions)
    \item All ALU ops (Int, FP, SIMD, DSP, everything)
-   \item All branches become predication targets (C.FNE added?)
+   \item All branches become predication targets (note: no FNE)
    \item C.MV of particular interest (s/v, v/v, v/s)
    \item FCVT, FMV, FSGNJ etc. very similar to C.MV
   \end{itemize}