From: lkcl <lkcl@web>
Date: Sun, 1 Aug 2021 22:07:10 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~548
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d60bf781da658be1e39b811f9b799baf6887a583;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 576bdf1a9..e5d84f4aa 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -6,3 +6,16 @@ Links
 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-August/003416.html>
 
 TODO
+| 0-1 |  2  |  3   4  |  description              |
+| --- | --- |---------|-------------------------- |
+| 00  |   0 |  ALL sz | normal mode                      |
+| 01  | VLI |  ALL sz | VLSET mode                      |
+
+Fields:
+
+* **sz**  if predication is enabled will put zeros into the src CR when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
+* **ALL** when set, all branch conditional tests must pass in order for
+the branch to succeed.
+* **VLI** In VLSET mode, VL is set equal (truncated) to the first branch
+which succeeds.  If VLI (Vector Length Inclusive) is clear, VL is truncated
+to *exclude* the current element, otherwise it is included.