From: lkcl <lkcl@web>
Date: Sat, 18 Sep 2021 13:04:22 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~73
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d6133d78516c2ea8da7c62789507f69a53e94d4d;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 12bdaf4b8..7d01166e6 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -167,7 +167,7 @@ are constructed:
 | EXT01  | RM    | 1 | RM    | 1 | RM       |
 | 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
 
-Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
+Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1
 instruction.  That instruction becomes "prefixed" with the SVP context: the
 Remapped Encoding field (RM).