From: Wesley W. Terpstra <wesley@sifive.com>
Date: Sat, 21 Jan 2017 06:38:27 +0000 (-0800)
Subject: xilinx pcie: put buffers before the outputs to the controller
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d61d86e08417ae182e7f2e8aabebc193941ce31a;p=sifive-blocks.git

xilinx pcie: put buffers before the outputs to the controller
---

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
index bd3b1ef..b82186c 100644
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
@@ -26,8 +26,8 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
   val intnode = IntSourceNode(1)
 
   val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
-  axi_to_pcie_x1.slave   := TLToAXI4(idBits=4)(slave)
-  axi_to_pcie_x1.control := AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control))
+  axi_to_pcie_x1.slave   := AXI4Buffer()(TLToAXI4(idBits=4)(slave))
+  axi_to_pcie_x1.control := AXI4Buffer()(AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)))
   master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
 
   lazy val module = new LazyModuleImp(this) {