From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Feb 2020 19:25:07 +0000 (-0800)
Subject: Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk
X-Git-Tag: working-ls180~814^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d625e399cb0b30d4a64085772f5f6d6011dfc0fd;p=yosys.git

Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk
---

diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v
index 995121597..4ae938827 100644
--- a/techlibs/xilinx/arith_map.v
+++ b/techlibs/xilinx/arith_map.v
@@ -36,12 +36,13 @@ module _80_xilinx_lcu (P, G, CI, CO);
 `ifdef _EXPLICIT_CARRY
 
 	wire [WIDTH-1:0] C = {CO, CI};
+	wire [WIDTH-1:0] S = P & ~G;
 
 	generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
 		MUXCY muxcy (
 			.CI(C[i]),
 			.DI(G[i]),
-			.S(P[i]),
+			.S(S[i]),
 			.O(CO[i])
 		);
 	end endgenerate
@@ -52,8 +53,8 @@ module _80_xilinx_lcu (P, G, CI, CO);
 	localparam MAX_WIDTH    = CARRY4_COUNT * 4;
 	localparam PAD_WIDTH    = MAX_WIDTH - WIDTH;
 
+	wire [MAX_WIDTH-1:0] S =  {{PAD_WIDTH{1'b0}}, P & ~G};
 	wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};
-	wire [MAX_WIDTH-1:0] PP = {{PAD_WIDTH{1'b0}}, P};
 	wire [MAX_WIDTH-1:0] C;
 	assign CO = C;
 
@@ -64,7 +65,7 @@ module _80_xilinx_lcu (P, G, CI, CO);
 			.CYINIT(CI),
 			.CI    (1'd0),
 			.DI    (GG[i*4 +: 4]),
-			.S     (PP[i*4 +: 4]),
+			.S     (S [i*4 +: 4]),
 			.CO    (C [i*4 +: 4]),
 			);
 		end else begin
@@ -73,7 +74,7 @@ module _80_xilinx_lcu (P, G, CI, CO);
 			.CYINIT(1'd0),
 			.CI    (C [i*4 - 1]),
 			.DI    (GG[i*4 +: 4]),
-			.S     (PP[i*4 +: 4]),
+			.S     (S [i*4 +: 4]),
 			.CO    (C [i*4 +: 4]),
 			);
 		end