From: Samuel Pitoiset Date: Fri, 2 Aug 2019 10:10:43 +0000 (+0200) Subject: ac: add has_clear_state to ac_gpu_info X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d62d2840c42d0eb3433c6c0c8bfe8d506c0475b9;p=mesa.git ac: add has_clear_state to ac_gpu_info Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák --- diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index b02f1471463..ed6e273c598 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -441,6 +441,12 @@ bool ac_query_gpu_info(int fd, void *dev_p, info->num_sdma_rings = util_bitcount(dma.available_rings); info->num_compute_rings = util_bitcount(compute.available_rings); + /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs + * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc. + * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. + */ + info->has_clear_state = info->chip_class >= GFX7; + /* Get the number of good compute units. */ info->num_good_compute_units = 0; for (i = 0; i < info->max_se; i++) diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 8418a62e387..69bac7252bf 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -58,6 +58,7 @@ struct radeon_info { uint32_t num_sdma_rings; uint32_t clock_crystal_freq; uint32_t tcc_cache_line_size; + bool has_clear_state; /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 34e65f11e0a..ca484fcc0fc 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -364,11 +364,6 @@ radv_physical_device_init(struct radv_physical_device *device, device->rad_info.family == CHIP_RENOIR; } - /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs - * on GFX6. - */ - device->has_clear_state = device->rad_info.chip_class >= GFX7; - device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8; /* Vega10/Raven need a special workaround for a hardware bug. */ diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 9bcb2baf97e..39d349b723c 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -282,7 +282,6 @@ struct radv_physical_device { bool has_rbplus; /* if RB+ register exist */ bool rbplus_allowed; /* if RB+ is allowed */ - bool has_clear_state; bool cpdma_prefetch_writes_memory; bool has_scissor_bug; bool has_tc_compat_zrange_bug; diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 32674d38bb9..d4369b5739a 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -159,6 +159,7 @@ void si_emit_graphics(struct radv_physical_device *physical_device, struct radeon_cmdbuf *cs) { + bool has_clear_state = physical_device->rad_info.has_clear_state; int i; /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */ @@ -168,7 +169,7 @@ si_emit_graphics(struct radv_physical_device *physical_device, radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1)); } - if (physical_device->has_clear_state) { + if (has_clear_state) { radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0)); radeon_emit(cs, 0); } @@ -177,7 +178,7 @@ si_emit_graphics(struct radv_physical_device *physical_device, si_set_raster_config(physical_device, cs); radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64)); - if (!physical_device->has_clear_state) + if (!has_clear_state) radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0)); /* FIXME calculate these values somehow ??? */ @@ -186,7 +187,7 @@ si_emit_graphics(struct radv_physical_device *physical_device, radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40); } - if (!physical_device->has_clear_state) { + if (!has_clear_state) { radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2); radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); @@ -194,19 +195,19 @@ si_emit_graphics(struct radv_physical_device *physical_device, if (physical_device->rad_info.chip_class <= GFX9) radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1); - if (!physical_device->has_clear_state) + if (!has_clear_state) radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0); if (physical_device->rad_info.chip_class < GFX7) radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | S_008A14_CLIP_VTX_REORDER_ENA(1)); - if (!physical_device->has_clear_state) + if (!has_clear_state) radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0); /* CLEAR_STATE doesn't clear these correctly on certain generations. * I don't know why. Deduced by trial and error. */ - if (physical_device->rad_info.chip_class <= GFX7 || !physical_device->has_clear_state) { + if (physical_device->rad_info.chip_class <= GFX7 || !has_clear_state) { radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1)); @@ -219,14 +220,14 @@ si_emit_graphics(struct radv_physical_device *physical_device, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); } - if (!physical_device->has_clear_state) { + if (!has_clear_state) { for (i = 0; i < 16; i++) { radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0); radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0)); } } - if (!physical_device->has_clear_state) { + if (!has_clear_state) { radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */ @@ -420,7 +421,7 @@ si_emit_graphics(struct radv_physical_device *physical_device, radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution); - } else if (!physical_device->has_clear_state) { + } else if (!has_clear_state) { radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14); radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16); } @@ -471,7 +472,7 @@ si_emit_graphics(struct radv_physical_device *physical_device, radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) | S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); - if (!physical_device->has_clear_state) { + if (!has_clear_state) { radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL, S_028004_ZPASS_INCREMENT_DISABLE(1)); } diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index b30839d25b5..f34286ecaec 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -372,7 +372,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx) ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS; /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */ - bool has_clear_state = ctx->screen->has_clear_state; + bool has_clear_state = ctx->screen->info.has_clear_state; if (has_clear_state) { ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs); diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 475c15c54ba..21e785dd44f 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1109,12 +1109,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws, S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers); } - /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs - * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc. - * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. */ - sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 && - sscreen->info.is_amdgpu; - sscreen->has_distributed_tess = sscreen->info.chip_class >= GFX8 && sscreen->info.max_se >= 2; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 7fd13cfa9e7..4630fff7357 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -491,7 +491,6 @@ struct si_screen { unsigned eqaa_force_coverage_samples; unsigned eqaa_force_z_samples; unsigned eqaa_force_color_samples; - bool has_clear_state; bool has_distributed_tess; bool has_draw_indirect_multi; bool has_out_of_order_rast; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 05844abe360..d5cdc660350 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5390,7 +5390,7 @@ static void si_init_config(struct si_context *sctx) { struct si_screen *sscreen = sctx->screen; uint64_t border_color_va = sctx->border_color_buffer->gpu_address; - bool has_clear_state = sscreen->has_clear_state; + bool has_clear_state = sscreen->info.has_clear_state; struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); if (!pm4)