From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 23 Feb 2011 21:10:48 +0000 (-0600)
Subject: ARM: Adds dummy support for a L2 latency miscreg.
X-Git-Tag: stable_2012_02_02~548
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d63020717c8a722eb2f5236eacd042cdee78769d;p=gem5.git

ARM: Adds dummy support for a L2 latency miscreg.
---

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 6a734a582..3bcb5c97d 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -143,6 +143,9 @@ let {{
           case MISCREG_BPIALL:
             return new WarnUnimplemented(
                     isRead ? "mrc bpiall" : "mcr bpiall", machInst);
+          case MISCREG_L2LATENCY:
+            return new WarnUnimplemented(
+                    isRead ? "mrc l2latency" : "mcr l2latency", machInst);
 
             // Write only.
           case MISCREG_TLBIALLIS:
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 13dec0add..fc04ce87d 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -381,6 +381,8 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
                     return MISCREG_PMINTENCLR;
                 }
             }
+        } else if (opc1 == 1) {
+            return MISCREG_L2LATENCY;
         }
         //Reserved for Branch Predictor, Cache and TCM operations
         break;
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index cf9da428a..90b4fd999 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -191,6 +191,7 @@ namespace ArmISA
         MISCREG_MVBAR,
         MISCREG_ISR,
         MISCREG_FCEIDR,
+        MISCREG_L2LATENCY,
 
 
         MISCREG_CP15_END,