From: lkcl <lkcl@web>
Date: Tue, 3 Sep 2019 16:14:02 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4165
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d6350c39c0c46c9a12edb7632db04aeeb5507791;p=libreriscv.git

---

diff --git a/simple_v_extension/vblock_format/discussion.mdwn b/simple_v_extension/vblock_format/discussion.mdwn
index 6ad14d4a8..baee7edf2 100644
--- a/simple_v_extension/vblock_format/discussion.mdwn
+++ b/simple_v_extension/vblock_format/discussion.mdwn
@@ -4,7 +4,7 @@ This VBLOCK mode effectively extends [[sv_prefix_proposal]] to cover multiple
 registers.  The basic principle: the "prefix" specifies which of source and
 destination registers are to be considered "vectors" (or scalars), however
 where in SVPrefix that applies to only one instruction, the "vector" tag
-designations *continue to cascade* into subsequent instructions within the
+designations *continue a limited cascade* into subsequent instructions within the
 VBLOCK.
 
 Its advantage over the main format is that the main format requires