From: lkcl Date: Fri, 12 Feb 2021 02:53:53 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~205 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d63dd0cb1f746b1b1c8f7570c93b3f9a76938a07;p=libreriscv.git --- diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn index 245fb40a1..2af407834 100644 --- a/3d_gpu/architecture/dynamic_simd.mdwn +++ b/3d_gpu/architecture/dynamic_simd.mdwn @@ -51,4 +51,4 @@ where behind the scenes the above laborious for-loops (conceptually) are created This means that nmigen needs to "understand" the partitioning, in m.If, m.Else and m.Switch, at the bare minimum. -Analysis of the internals of nmigen shows that m.If, m.Else and m.Switch are all redirected to `Value.cases'. Within that function Mux and other "global" functions (similar to python operator functions). The hypothesis is therefore proposed that if `Value.mux` is added in an identical way to how `operator.add` calls `__add__` this may turn out to be all that (or most of what) is needed. +Analysis of the internals of nmigen shows that m.If, m.Else and m.Switch are all redirected to `Value.cases`. Within that function Mux and other "global" functions (similar to python operator functions). The hypothesis is therefore proposed that if `Value.mux` is added in an identical way to how `operator.add` calls `__add__` this may turn out to be all that (or most of what) is needed.