From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 24 May 2020 15:17:30 +0000 (-0700)
Subject: xaiger: do not derive cells
X-Git-Tag: working-ls180~540^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d64df216302bab5b7c5047bbbcb0e3cd82f1ec2d;p=yosys.git

xaiger: do not derive cells
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 69797ceaf..6b910eecd 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -248,6 +248,7 @@ struct XAigerWriter
 				auto it = cell->attributes.find(ID::abc9_box_seq);
 				if (it != cell->attributes.end()) {
 					log_assert(!cell->has_keep_attr());
+					log_assert(cell->parameters.empty());
 					int abc9_box_seq = it->second.as_int();
 					if (GetSize(box_list) <= abc9_box_seq)
 						box_list.resize(abc9_box_seq+1);
@@ -260,13 +261,6 @@ struct XAigerWriter
 						continue;
 				}
 
-				if (!cell->parameters.empty()) {
-					auto derived_type = inst_module->derive(design, cell->parameters);
-					inst_module = design->module(derived_type);
-					log_assert(inst_module);
-					log_assert(inst_module->get_blackbox_attribute());
-				}
-
 				if (!timing.count(inst_module->name))
 					timing.setup_module(inst_module);
 				auto &t = timing.at(inst_module->name).arrival;