From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 3 May 2023 10:59:13 +0000 (+0100)
Subject: reduce line width
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d64fb05be0f30e7ebfb439a41fc9c077dfc08259;p=libreriscv.git

reduce line width
---

diff --git a/conferences/siliconsalon2023/siliconsalon2023.tex b/conferences/siliconsalon2023/siliconsalon2023.tex
index 2a9956bcb..39ba81932 100644
--- a/conferences/siliconsalon2023/siliconsalon2023.tex
+++ b/conferences/siliconsalon2023/siliconsalon2023.tex
@@ -121,7 +121,7 @@
    \item Shift by 64-bit is just "pick a register"
    \item Add a 2nd input register with what needs to be shifted IN\\
          (64-bit carry in)
-   \item Add a 2nd output register saving what normally gets thrown away\\
+   \item Add 2nd output saving what normally gets thrown away\\
    		(64-bit carry-out)
    \item Again: a chain of these performs Vector-by-Scalar shift
   \end{itemize}